Synchronous pipelined burst memory and method for operating same

Details Synchronous pipelined burst memory and method for operating same Synchronous pipelined burst memory and method for operating same

1998-04-17

1999-07-13

Le, Vu A.

Static information storage and retrieval

Addressing

Byte or page addressing

365233, G11C 700

Patent

active

059236159

ABSTRACT:
A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which latches a burst address during a first cycle of a periodic clock signal. The burst address is driven to an input of an asynchronous memory core (40), but output data from the asynchronous memory core (40) is not latched until a third cycle of the periodic clock signal which occurs after a second cycle of the periodic clock signal which is immediately subsequent to the first cycle. The memory (20) outputs successive data elements of the burst during consecutive cycles of the periodic clock signal to complete the burst cycle.

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Motorola, Inc. Mar. 16, 1998 Semiconductor Technical Data, "Advance Information 64K .times. 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM", MCM63P636, pp. 1-26.

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