Synchronous parallel/serial converter

Details Synchronous parallel/serial converter Synchronous parallel/serial converter

2007-07-17

2007-07-17

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

11331478

ABSTRACT:
A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

REFERENCES:
patent: 6259387 (2001-07-01), Fukazawa
patent: 6801144 (2004-10-01), Matsudera et al.
patent: 2003/0095057 (2003-05-01), Gredone et al.
patent: 10 2004 026 526 (2005-01-01), None
patent: 61030122 (1986-02-01), None

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