Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-17
2001-03-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S230030
Reexamination Certificate
active
06198660
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to static memories, and, more particularly, to synchronous multilevel non-volatile memories and associated methods.
BACKGROUND OF THE INVENTION
It is known that the most recent developments in the field of computers have produced microprocessors which operate at ever higher clock frequencies. These processors must of course be interfaced with non-volatile memories, such as EPROM and FLASH memories. However, the increase in the clock frequency of processors has not been accompanied by a correlated increase in the operating frequency of non-volatile memories, which currently operate at much lower frequencies, at most 20 MHz.
Accordingly, the performance of processors on the motherboard of computers which must interface with the non-volatile memories via a bus depends on the operating frequency of the non-volatile memories and therefore such performance is decreased. Likewise, hard disk drives contain non-volatile memories which, as mentioned, have an operating speed which also decreases performance of the hard disk drives.
Accordingly, the trend is to obtain improved performance from memories via particular architectural
5
techniques which have the drawback that they require additional silicon areas which increases the costs of the system. Currently, a good technique is the so-called burst method, which however requires an additional silicon area, leading to a cost increase.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous multilevel non-volatile memory in which the operating speed of the memory is substantially doubled with respect to known non-volatile memories. Another object of the present invention is to provide a synchronous multilevel non-volatile memory in which the increase in the performance of the memory is not accompanied by an increase in occupied silicon area.
Another object of the present invention is to provide a synchronous multilevel non-volatile memory in which the storage capacity is the same, in contrast with a higher operating speed and with a silicon area occupation similar to that of conventional memory devices. Another object of the present invention is to provide a method for reading a synchronous multilevel non-volatile memory which allows an increase in the reading performance of the memory. Another object of the present invention is to provide a synchronous multilevel non-volatile memory which is highly reliable, relatively easy to manufacture and at competitive costs.
These objects and others which will become apparent hereinafter are achieved by a method for reading a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different planes of the multilevel memory and plane addresses which define the plane on which the memory cell defined by a memory cell address is to be read. The method includes switching the plane address at a preset time interval after the switching of a memory address and at the highest possible switching frequency, and reading the content of a memory location, from the memory, which corresponds to the memory address on planes alternatively indicated by the switching of the plane address.
REFERENCES:
patent: 5297148 (1994-03-01), Harrari et al.
patent: 5375097 (1994-12-01), Reddy et al.
patent: 5497354 (1996-03-01), Sweha et al.
patent: 5691956 (1997-11-01), Chang et al.
patent: 0913834A1 (1996-07-01), None
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Le Vu A.
STMicroelectronics S.r.l.
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