Synchronous mirror delay with reduced delay line taps

Details Synchronous mirror delay with reduced delay line taps Synchronous mirror delay with reduced delay line taps

2001-05-25

2003-05-27

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000

Reexamination Certificate

active

06570813

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly, to synchronous mirror delay circuits with delay line taps for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.
BACKGROUND OF THE INVENTION
Memory access speed and the resulting data transfer bandwidth has been a typical bottleneck in computer systems and other digital applications. A newer type of dynamic random access memory (DRAM), known as a synchronous DRAM or SDRAM, has been developed to provide faster operation and improve memory access times. SDRAMs are designed to operate synchronously with the system clock with input and output data synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices memory, access is still a limiting factor, and there is a need for still faster memory devices. With this in mind, double data rate (DDR) SDRAMs were developed to allow data transfers on both the rising and falling edges of the system data clock, providing twice the operating speed of the conventional SDRAM. Thus, DDR SDRAM provides up to twice as much data bandwidth as the conventional SDRAM for a given data clock. In addition, as with SDRAM, DDR SDRAMs are also capable of providing bursts of data at a high-speed data rate.
As clock frequencies increase, it is desirable to have less uncertainty when valid data is available on the output of the memory in DDR SDRAM. As shown in
FIG. 1
, due to the high speed data transfers DDR SDRAMs use a data strobe signal (DQS)
100
to register the data (DQ)
104
on both edges of the system clock
102
. This allows the receiving system to improve latching the presented data under the timing constraints of modern high speed memory data transfers. According to industry standards, when data is being received by the DDR SDRAM, the DQS has a known latency
106
,
108
which varies between 3/4 of the system clock cycle (minimum latency) to 5/4 of the clock cycle (maximum latency). Because of this variability, and the above mentioned timing constraints of modem high speed memory data transfers, DDR SDRAMs utilize a clock skew adjustment circuit to drive this latency variability to as close to zero as feasible and synchronize the DQS signal and output data signals to the system data clock.
A common clock skew adjustment circuit utilized in DDR SDRAM is a delay locked loop (DLL), shown in FIG.
2
. DLL's generally consist of a delay line
200
of individual delay elements, that generates a replica of a clock signal which is compared against the input clock signal. The clock signal loaded into the delay line
200
is iteratively adjusted until a match or “lock” is achieved. The delay line
200
is coupled to a shift register
202
that loads data into the delay line
200
to begin generation of the clock pulse signal. The individual delay elements (not shown) in the delay line typically comprise NAND gates that are coupled to an inverter. The shift register
202
is adjusted by a phase detector
204
that compares the replicated clock pulse against the external clock pulse. The phase detector
204
increments or decrements the shift register
202
a fixed amount up and down for each clock cycle, allowing the DLL to iterate until a “lock” with the input external clock signal is attained. When the circuit containing the DLL is powering up or coming out of a low power mode it is not uncommon for 50 or more clock cycles to pass until the feedback based DLL attains a lock with the external clock, delaying initial access to the memory.
Another clock skew adjustment circuit utilized in DDR SDRAM, that is not feedback based, is a synchronous mirror delay (SMD). A SMD circuit can attain a lock with the external clock signal in as few as two clock cycles. This ability greatly decreases the time to first access when a DDR SDRAM comes out of a low power mode. A SMD circuit generally includes two delay lines and an accompanying control circuit, all of which must be of a length sufficient to accommodate the full time period of the clock pulse to be matched. Any additional space that would be required to allow an adequate adjustment range of the clock period must also be incorporated into the SMD circuit, further increasing the SMD circuit size. Therefore, an SMD circuit generally requires more space to implement on the integrated circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce clock period matching, or lock times, in integrated circuits with clock skew adjustment circuits. Additionally, there is a need to reduce SMD circuit size in integrated circuits.
SUMMARY OF THE INVENTION
The above-mentioned problems with SMD circuits, particularly with DDR SDRAM that compensate for the latency variation in the DQS signal, and other problems, are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an SMD circuit comprises a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
In another embodiment, an SMD circuit comprises a clock source, a data path model coupled to the clock source, a first delay segment coupled to the data path model, a forward delay line coupled to the first delay segment, an SMD control circuit coupled to the forward delay line and to the clock source, and a backward delay line coupled to the SMD control circuit, the clock source, and to a second delay segment.
In a further embodiment, an integrated circuit comprises a clock input buffer coupled to receive a clock signal with a time period, a delay segment coupled to the clock input buffer, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and to the clock input buffer, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
In yet another embodiment, a memory device comprises an address interface, a data interface, a control interface, and an SMD clock recovery and skew adjustment circuit. The SMD clock recovery and skew adjustment circuit comprises a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
In yet a further embodiment, a DDR memory device interface circuit comprises a data interface, a DQS signal interface, a data latch coupled to the data interface, and an SMD clock recovery and skew adjustment circuit coupled to the data latch and coupled to the DQS signal interface. The SMD clock recovery and skew adjustment circuit comprises a clock input buffer coupled to receive a clock signal with a time period, a data path model coupled to the clock input buffer, a first delay segment coupled to the data path model, a forward delay line coupled to the first delay segment, an SMD control circuit coupled to the forward delay line and to the clock input buffer, and a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.
A method of synchronizing with a clock signal comprises receiving a clock signal having a clock signal time period, subtracting a first time period equivalent to a real data path, subtracting a second time period that is a static component, measuring a remaining component of the clock sign

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