Synchronous mirror delay circuit with adjustable locking range

Details Synchronous mirror delay circuit with adjustable locking range Synchronous mirror delay circuit with adjustable locking range

2005-08-23

2005-08-23

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S141000

Reexamination Certificate

active

06933758

ABSTRACT:
A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

REFERENCES:
patent: 6222792 (2001-04-01), Hanzawa et al.
patent: 6396322 (2002-05-01), Kim et al.
patent: 6489824 (2002-12-01), Miyazaki et al.
patent: 6570419 (2003-05-01), Hanzawa et al.
patent: 6617894 (2003-09-01), Yoon et al.
patent: 2004/0178836 (2004-09-01), Kim et al.

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