Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-05-25
2004-10-19
Yao, Kwang Bin (Department: 2667)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S516000
Reexamination Certificate
active
06807180
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention refers to the clock recovery in the transport of constant bit rate (CBR) services, suited for the implementation of the adaptation Layer 1 in asyncronous transfer mode (ATM). This adaptation layer is used for the transport of CBR services over an ATM network.
More precisely, this invention relates to a synchronous method of clock recovery in the transfer of CBR services over ATM network, based on a duty cycle timing information (DCTI).
Three methods of clock recovery in the transport of CBR services over an ATM network are presently known: synchronous frequency encoding technique (SFET); time stamp method with common network timing; and the synchronous residual time stamp (SRTS) method, which avoids the drawbacks and encompasses the advantages of the previous two ones. The said methods are respectively reported in “Synchronous Frequency Encoding Technique for Circuit Emulation”, by R. C. Lau in SPIEconf. on Visual Proc. and image Comm., Pages 160-171, September 1989; in “Proposed Method to Provide the Clock Recovery Function for Circuit Emulation” in CCITT SG XVIII French contribution D.1020, December 1992; and in U.S. Pat. No. 5,260,978, the contents of all of them being herein incorporated as part of this specification.
Although the SRTS method—which is employed nowadays—gives rise to acceptable results, the search for improved methods, able to provide the clock recovery in a more satisfactory way, is always very attractive.
This invention refers to a synchronous method for the clock recovery, which is able to ensure better performances than the ones employed according to the above referenced prior art, resulting in important advantages.
SUMMARY OF THE INVENTION
The synchronous DCTI method for clock recovery according to the present invention is substantially characterised in that the square wave related to the source frequency is compared to the square wave related to the network frequency by using an exclusive OR, in order to get a signal from which duty cycle is obtained, and in that information which is necessary and sufficient to recover the source clock, when the network clock is known, is transported to the receiver by the duty cycle.
In the said method, the duty cycle of said signal is obtained by a generator which creates the actual duty cycle of the signal or its complementary to 1, in order to make the duty cycle created at the transmitter comparable to the one created at the receiver.
It should also be understood that the method according to the invention:
uses a generator of duty cycle at the transmitter and a generator of a control parameter, an oscillating system and a generator of duty cycle, which is identical to the transmitter one, at the receiver;
makes the generator of the control parameter receive the duty cycles from the transmitter and from the receiver and create by difference a parameter which feeds the oscillation system to obtain the correction of the arrival frequency in an oscillator;
makes the generator of the control parameter use the difference of the duty cycles, or the complementary to 1 of the modulus of such a difference, in the calculation of said parameter and makes the generator take into consideration two values subsequent in time of the obtained signal, in order to feed with the difference signal the oscillation system;
limits the difference signal, in the oscillation system, applies a gain factor and sums the present output to the previous one, in order to convert subsequently the obtained signal from digital to analog and to drive by means of the latter an oscillator which provides the recovered source frequency.
It is furthermore important to realise that, according to the synchronous method of the invention, the signal which is to be converted is formed by a number of bit, provided by
B
=
⌈
log
2
(
Δ
f
&LeftBracketingBar;
K
&RightBracketingBar;
·
2
b
+
1
)
⌉
wherein &Dgr;f is the desired capture range of the frequency around the nominal value of the frequency of said oscillator, k is the gain of the control system and b is the number of bits that has been chosen to represent the duty cycle.
REFERENCES:
patent: 4809306 (1989-02-01), Somer
patent: 5812618 (1998-09-01), Muntz et al.
patent: 5844891 (1998-12-01), Cox
patent: 6111878 (2000-08-01), Powell
patent: 6144714 (2000-11-01), Bleiweiss et al.
patent: 6269127 (2001-07-01), Richards
patent: 6606324 (2003-08-01), Stracca
patent: 0 637 137 (1995-02-01), None
BT Technology Journal, vol. 13, No. 3, Jul. 1, 1995, pp. 35-45, XP000543496, M. Mulvey et al., “Timing Issues of Constant Bit Rate Services Over ATM”.
Countdown to the New Milennium, Institute of Electrical and Electronics Engineers, Phoenix, Arizona, vol. 2, Dec 2, 1991, pp. 402-406, XP000326005, Loau Chii-Min et al., “PHDPLL For Sonet Desynchronizer”, Count.
Telefonaktiebolaget LM Ericsson (publ)
Yao Kwang Bin
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