Synchronous memory with dual sensing output path each of which i

Details Synchronous memory with dual sensing output path each of which i Synchronous memory with dual sensing output path each of which i

1997-12-10

1999-05-04

Le, Vu A.

Static information storage and retrieval

Addressing

Sync/clocking

365205, 365207, 36518905, G11C 700

Patent

active

059011106

ABSTRACT:
Disclosed is a synchronous memory device with a dual sensing output path having two data paths, each of which has a latch circuit and a sense amplifier. The synchronous memory device includes a first data reading means for amplifying and latching the data from memory cells in response to odd clock signals, a second data reading means coupled in parallel to the first data reading means for amplifying and latching the data from memory cells in response to the even clock signals, and a clock signal generating means for alternatively generating even clock signals and odd clock signals. According the second data reading means outputs to an output buffer the latched data therein while the second data reading means amplifies the data. As a result, the synchronous memory device according to the present invention may reduces the cycle time to read the cell data by up to 33%.

REFERENCES:
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 5015891 (1991-05-01), Choi
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5311471 (1994-05-01), Matsumoto et al.

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