Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-03-08
1995-03-28
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sync/clocking
365194, 365240, 36518912, G11C 800
Patent
active
054023890
ABSTRACT:
A synchronous memory (20) has parallel data output registers (34) and a dummy path (46). The output data from a memory array (22) is provided to the parallel output registers (34). The output registers (34) provide two parallel, interleaved, output data paths. The data in each path changes every other cycle of a clock signal. Dummy path (46) contains delay elements that model a propagation delay for a data path of the memory (20) during a read cycle. Using parallel data output registers (34) increases a time in which data is valid during the read cycle. The dummy path (46) tracks the output data signal in terms of process, power supply and temperature variations to ensure that the correct data is acquired during the read cycle.
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Flannagan Stephen T.
Jones Kenneth W.
Kung Roger I.
Hill Daniel D.
Motorola Inc.
Popek Joseph A.
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