Synchronous memory device with reduced address pins

Details Synchronous memory device with reduced address pins Synchronous memory device with reduced address pins

2002-07-22

2004-04-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

26, 26

Reexamination Certificate

active

06717884

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a synchronous memory device capable of reducing the number of address pins by changing address input.
DESCRIPTION OF THE RELATED ARTS
Recently, synchronous semiconductor memory devices, such as double data rate (DDR) SDRAMs and Rambus DRAMs, have been proposed as next generation memory devices because these synchronous semiconductor memory devices implement higher speed operation than asynchronous semiconductor memory devices.
Typically, a central processing unit (CPU) combines control signals in order for the memory to recognize a command. For example, when a command, such as a chip selection signal or a write enable signal, is enabled, the memory recognizes this command as a control signal for a write operation. Control signals transmitted from the CPU include chip selection signal, write enable signal, column address strobe signal, row address strobe signal and clock enable signal. These control signals are called “command signals” because a command is created by a combination of these control signals. Accordingly, pins required to apply these control signals to the memory are called “command pins.”
As mentioned above, the memory chip has a plurality of command pins and even more address pins for specifying a memory cell in which the command is executed.
FIG. 1
is a schematic diagram of command and address pins of a conventional synchronous memory device.
The conventional synchronous memory device in
FIG. 1
has fourteen address pins A
0
to A
13
, five command pins CS, RAS, CAS, WE and CKE and two clock pins CLK and CLKz. Input signals are buffered in input buffers
10
wherein the input buffers
10
are coupled to the pins on one side and to latch circuits
16
on the other.
Each latch circuit
16
latches address or command signal in response to an internal clock signal clkp
2
from a clock pulse generator
14
. That is, the latch circuits
16
coupled to the address pins A
0
to A
13
output the buffered address signals <at
0
:at
13
>in response to the internal clock signal clkp
2
and the latch circuits
16
coupled to the command pins CS, RAS, CAS, WE and CKE output the buffered command signals cs
2
, cs
2
z
, ras
2
, ras
2
z
, cas
2
, cas
2
z
, we
2
, we
2
z
, cke
2
and cke
2
z
in response to the internal clock signal clkp
2
.
On the other hand, the internal clock signal clkp
2
, which is used for controlling the latch circuits
16
, is generated by the clock pulse generator
14
. The clock pulse generator
14
receives an internal clock signal iclk from a clock buffer
12
which receives the external clock signals.
In the synchronous memory device mentioned above, the latched address and command signals are outputted at a falling edge of the internal clock signal iclk. The command signals are inputted into the memory via the command pins and the address signals are inputted into the memory via the address pins. Accordingly, to receive the address and command signals simultaneously, pins for the address and command signals are independently provided.
Meanwhile, the integration of the memory continuously increases and this denotes an increase in the number of memory cells. As a result, much more address bits are required to select one among many cells.
Notwithstanding the diminishment of the design rule based on the improved semiconductor memory processes, the package technology does not act up to such a development in integration. Accordingly, the number of pins in memory devices inevitably increases, thereby increasing the chip size.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a synchronous memory device capable of reducing the number of address pins by changing address input.
It is another object of the present invention to provide a synchronous memory device which reduces power consumption by reducing the number of input buffers.
In accordance with an aspect of the present invention, there is a synchronous memory device receiving various signals from an external controller, including at least one common pin receiving a first signal and a second signal; latch circuits coupled to the common pin, wherein the latch circuits latch the first and second signals and one of the latch circuits selectively outputs the first or second signal in response to first and second internal clock pulses; and clock pulse generating means for receiving the external clock signal and for producing the first and second internal clock pulses using the external clock signal.
In accordance with yet another aspect of the present invention, there is a synchronous memory device receiving various signals from an external controller, including: a plurality of address pins for receiving address signals; a plurality of address/command common pins, each of which receiving an address signal and a command signal; a plurality of input buffers, each coupled to a corresponding address pin or a corresponding address/command common pin for buffering an address or a command signal; a plurality of first latch circuits coupled to the buffers respectively, wherein each of the first latch circuits latches the address signal and outputs the address signal in response to a first internal clock pulse; a plurality of second latch circuits coupled to the buffers, respectively, wherein each of the second latch circuits latches the command signal and outputs the command signal in response to a second internal clock pulse; and a clock pulse generating means for receiving the external clock signal and for producing the first and second internal clock pulses from the external clock signal.


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