Synchronous memory device

Details Synchronous memory device Synchronous memory device

2006-02-07

2006-02-07

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S198000, C365S230030, C365S230050

Reexamination Certificate

active

06996027

ABSTRACT:
A synchronous memory device and a synchronous multi-port memory device preventing a skew between data and data strobe signal according to data transmission path is disclosed. In order to eliminate such a position dependence, the synchronous memory device and the synchronous multi-port memory device adopt a scheme of transmitting the data strobe signal together with the data. If a data driving block transmits the data capture pulse together with the data, the data and the data capture pulse pass the same delay without regard to the data transmission/reception blocks, thus preventing the occurrence of the skew. In other words, the present invention adopts a source synchronization scheme, which is used at an outside of the conventional synchronous DRAM, into the memory device. Specifically, the present invention can be applied to a synchronous multi-port memory device having a plurality of independent ports.

REFERENCES:
patent: 6359815 (2002-03-01), Sato et al.
patent: 2004/0076044 (2004-04-01), Nowshadi
patent: 2005/0137966 (2005-06-01), Mungula et al.

Affiliated with

Also associated with

Rating

Synchronous memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3664531