Synchronous memory circuit

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S233160, C365S233170, C365S233100

Reexamination Certificate

active

07729198

ABSTRACT:
A semiconductor integrated circuit device including a memory circuit with both high access efficiency and high memory efficiency in a simple configuration is provided. In a memory read control circuit, burst length is changed based on whether or not a read instruction is issued at a cycle after a cycle at which a read instruction /R is issued. And, in a memory write control circuit, burst length is changed based on whether or not a write instruction is issued at a cycle before a cycle at which a write instruction /W is issued.

REFERENCES:
patent: 6128233 (2000-10-01), Yu et al.
patent: 6556506 (2003-04-01), Naven
patent: 6674686 (2004-01-01), Noh et al.
patent: 6999376 (2006-02-01), Roohparvar
patent: 2001/0036116 (2001-11-01), Kubo et al.
patent: 2000-90665 (2000-03-01), None
patent: 2000-306379 (2000-11-01), None

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