Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-10-29
2010-06-01
Lam, David (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233160, C365S233170, C365S233100
Reexamination Certificate
active
07729198
ABSTRACT:
A semiconductor integrated circuit device including a memory circuit with both high access efficiency and high memory efficiency in a simple configuration is provided. In a memory read control circuit, burst length is changed based on whether or not a read instruction is issued at a cycle after a cycle at which a read instruction /R is issued. And, in a memory write control circuit, burst length is changed based on whether or not a write instruction is issued at a cycle before a cycle at which a write instruction /W is issued.
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patent: 2000-306379 (2000-11-01), None
Hasegawa Masatoshi
Nakayama Michiaki
Sakamoto Masatoshi
Hitachi , Ltd.
Lam David
Miles & Stockbridge P.C.
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