Synchronous memory allowing early read command in write to read

Details Synchronous memory allowing early read command in write to read Synchronous memory allowing early read command in write to read

1996-02-16

1996-12-24

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 365235, 3652385, G11C 800

Patent

active

055879616

ABSTRACT:
A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.

Affiliated with

Also associated with

Rating

Synchronous memory allowing early read command in write to read does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous memory allowing early read command in write to read , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous memory allowing early read command in write to read will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1183462