Synchronous memory

Details Synchronous memory Synchronous memory

2000-02-04

2001-06-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S207000

Reexamination Certificate

active

06249482

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous memory, such as of the single port random access type.
2. Description of the Prior Art
FIG. 1
of the accompanying drawings illustrates a known type of static random access memory (RAM), perhaps more descriptively also known as a read/write memory. The memory
1
comprises a core
2
containing an array of memory cells such as
3
arranged as rows and columns. The rows of memory cells
3
are connected via respective row address lines such as
4
to a row decoder
5
. The column of memory cells
3
are connected via respective column address lines or pairs of lines such as
6
to a column decoder and multiplexer
7
. The or each output of the column decoder and multiplexer
7
is connected to the input of a respective one of a set of sense amplifiers
8
. The sense amplifiers
8
are connected to input/output cells
9
having inputs for receiving data signals D to be read into or stored in the memory
1
and outputs Q for data read from the memory
1
.
The memory
1
has an address input “adr” in the form of a parallel bus connected to a plurality of latches
10
. The memory
1
also has a clock input clk for controlling timing of the memory connected to the sense amplifiers
8
via a delay circuit
11
. The memory also has inputs for a write enable signal web and an output enable signal “oeb”.
FIG. 2
is a detailed timing diagram illustrating operation of the memory shown in FIG.
1
. In addition to the signals already identified,
FIG. 2
illustrates a sense amplifier enable signal “sense”, row select and column select signals “wl/col” as supplied to the row decoder
5
and the column decoder and multiplexer
7
, precharge control signals “prech” for precharging the row and column address lines, multiplexer output signals “muxout” occurring within the column decoder and multiplexer
7
, and signals “bitlines” supplied to the memory cells
3
during write cycles and received at the inputs of the sense amplifiers
8
during read cycles.
The left part of
FIG. 2
illustrates a write cycle. This is initiated when a new address “adr” is supplied to the memory and latched in the latches
10
. Before writing to the memory cells
3
can begin, it is necessary to wait for a period known as an “address setup time” so that the correct addressing signals appear in the row decoder
5
and the column decoder and multiplexer
7
at the “edge” of the core
2
. However, the signals are not yet supplied to the core
2
. During the address set up time, the data D to be written into the memory are supplied and a “data setup time” has to be allowed, again, for the fresh data to be ready to present to the core
2
. The address and data set up times end when a clock pulse “clk” is received for activating the write operation. The arrival of the active clock pulse allows the signals to propagate on the address lines
4
and
6
into the core
2
so that the fresh data are written into the addressed or selected memory cells
3
. However, there is a delay between the start of the clock pulse “clk” and the row and column select signals “wl/col” propagating into the core
2
. After this delay, the multiplexer ouput “muxout” and the signals “bitlines” to the memory cells appear so that the fresh data are written into the selected memory cells
3
.
After a predetermined time, the row decoder
5
and the column decoder and multiplexer
7
remove the select signals “wl/col” from the edges of the core
2
. A precharge signal “prech” is then used to precharge the address lines
4
and
6
to any desired precharge, such as zero charge. The clock signal “clk” then goes low and the memory is then ready for the next cycle.
The right part of
FIG. 2
illustrates a read cycle which, again, begins with a new address signal “adr” being applied to the address input of the memory
1
. The active low write enable signal “web” goes high shortly after the new address has been supplied so that the memory
1
is ready for a read operation. After the address setup time, which is the same as that illustrated during the write cycle in
FIG. 2
, the clock signal “clk” goes high and the select signals “wl/col” are supplied to the edge of the core
2
. When the stored value of one of the memory cells
3
corresponds to a different charge state of the column address lines
6
, the capacitance of the lines
6
and the various other parasitic capacitances (and inductances) through the read path via the multiplexers to the differential inputs of the sense amplifiers have to be charged to a level such that the differential voltage input at the inputs of the sense amplifiers
8
is sufficient for the outputs of the sense amplifiers
8
to produce the correct signal level corresponding to the stored data. The necessary signal margin is indicated in the bottom waveform of
FIG. 2
, at which time the sense amplifiers
8
are enabled by the signal “sense”.
The read cycle ends when the clock signal “clk” goes low and another precharge operation is carried out prior to the next memory cycle.
During a read cycle, the leading edge of the clock signal “clk” must follow a change in the address “adr” by a sufficiently long address setup time for the row decoder
5
and the column decoder and multiplexer
7
to be ready to access the core
2
correctly. Thus, the row decoder
5
must be ready to supply a row select signal “wl” and the column decoder and multiplexer
7
must be set up ready to access the correct column before the clock signal “clk” can become active. The read access time shown in
FIG. 2
corresponds to the active phase of the clock signal “clk”. Once the clock signal “clk” has gone high to become active, time must be allowed for the select signals “wl/col” to propagate into the core and for the sense amplifier input to achieve the necessary signal margin for the worst possible combination of elements causing delays. The sense signal “sense” therefore becomes active after a predetermined or self-timed delay following the rising edge of the clock signal clk. Also, the duration of the enable signal “sense” is self-timed.
FIG. 3
illustrates part of the memory
1
in a more detailed schematic manner so as to illustrate the processes during a read cycle including those which are self-timed. At a time t
1
, the address “adr” changes. Following the address setup time to allow the circuits within the row decoder
5
and the column decoder and multiplexer
7
to stabilize, the clock signal “clk” rises at time t
2
. The clock signal “clk” directly clocks the row decoder
5
and the column decoder and multiplexer
7
so that the row select signal “wl” is supplied to the selected row address electrode
4
and the column select signal “col” connects the column address lines
6
of the selected memory cell or cells
3
(only one illustrated in
FIG. 3
) through the multiplexing to the inputs of the corresponding sense amplifier. This phase of operation is complete at time t
3
, after which the charge stored in the memory cell
3
representing the stored bit of data can begin to charge the column address lines
6
and any parasitic capacitances within the column decoder and multiplexer
7
. Similarly, the output signals from the column decoder and multiplexer
7
begin charging the differential inputs of the sense amplifier
8
. The differential signal d at the input of the sense amplifier
8
is illustrated in
FIG. 4
for a “worst case” condition where the various circuit elements require the longest time to be charged to the minimum signal margin for causing the sense amplifier
8
to switch its output to the correct value. This margin is achieved at a time t
4
when the delay circuit
11
supplies the sense amplifier enable signal “sense” to the sense amplifiers
8
.
In order for a read cycle to operate correctly, the time period from t
1
to t
2
must be sufficient for the row decoder
5
and column decoder and multiplexer
7
to settle correctly after a change of address “adr”. The clock pulses “clk” must therefore be delayed with respect

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