Synchronous low voltage differential I/O buss

Details Synchronous low voltage differential I/O buss Synchronous low voltage differential I/O buss

2008-01-01

2008-01-01

Ly, Anh-Vu H. (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C709S208000

Reexamination Certificate

active

10099315

ABSTRACT:
The present invention is directed to a synchronous I/O interface buss system. The system includes a master-buss controller that generates a system timing signal. The master-buss controller transmits a time-division multiplexed (TDM) slave output data signal and receives a time-division multiplexed (TDM) slave input data signal. The TDM slave output data signal and the TDM slave input data signal are synchronous relative to the system timing signal. A buss is coupled to the master-buss controller. The buss propagates the system timing signal, the TDM slave output data signal, and the TDM slave input data signal. At least one slave device is coupled to the buss. The at least one slave device is in synchronicity with the system timing signal. The at least one slave device demultiplexed slave device output data in device-ready format from the TDM slave output data signal during a predetermined output data signal time slot. The at least one slave device also multiplexes slave input data in file-ready format into the TDM slave input data signal during a predetermined input data signal time slot.

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