Synchronous logic array circuit with dummy signal lines for cont

Details Synchronous logic array circuit with dummy signal lines for cont Synchronous logic array circuit with dummy signal lines for cont

1987-05-21

1988-07-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307469, 307481, 307269, 307594, 307606, H03K 19177, H03K 17284

Patent

active

047602902

ABSTRACT:
In the present invention, an improved synchronous PLA circuit is disclosed. The PLA circuit is responsive to a single clock cycle. The PLA circuit has no internal or output glitches. Further, the PLA circuit uses less power since there are no internal or output glitches. The PLA circuit requires less area since metal lines do not have to carry as much power and do not have to be as wide as the prior art PLA circuits. Since less power is used, long term reliability is improved due to reduced heating stress and reduced current density stress (metal electromigration, etc.). The PLA circuit consists of two logic arrays and four dummy signal delay lines. When a clock signal gates the input signals into the logic array, it also simultaneously generates a dummy signal. The dummy signal propagates through adjacent dummy signal delay lines that parallel each logic array dimension and match the longest or worst case, delay through the logic array. Said delay lines having a plurality of interconnected single transistors with the number of transistors in each respective delay line being equal to the maximum number of transistors in each respective internal array for each respective dimension. Upon the dummy signals arriving at specific locations, control signals are generated which gate the output from each logic array.

REFERENCES:
patent: 4611133 (1986-09-01), Peterson et al.
patent: 4668880 (1987-05-01), Shoji
patent: 4687959 (1987-08-01), Eitrheim et al.
patent: 4692637 (1987-09-01), Shoji
patent: 4697105 (1987-09-01), Moy
patent: 4700088 (1987-10-01), Tubbs

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