Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-05-20
2001-06-12
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S290000, C360S051000
Reexamination Certificate
active
06246733
ABSTRACT:
TECHNICAL FIELD
This invention relates to the detection of data which has synchronous data recording characteristics, such as partial response maximum likelihood (PRML) data, and, more particularly, to the detection of such data with an asynchronous data detection channel.
BACKGROUND OF THE INVENTION
The recording of data on a moving memory device, such a magnetic data storage media, is best accomplished by means of NRZ (non-return to zero) recording in which the data is self-clocking without separate clock signals. Thus, only data is recorded in the media and no space is “wasted” for the recording of clock signals. To accomplish such recording, the recording signal in a track comprises a sequence of regular intervals, wherein a recorded signal (such as a transition between magnetic polarities) appearing in an interval is designated as a “1” and the absence of a signal in an interval is designated as a “0”. The location in each interval at which a recorded signal (transition) may appear or be absent from is called a synchronous location.
A method for encoding and detecting such data is a partial response maximum likelihood (PRML) data reproduction method. The data is coded into a run-length limited code and modulated in accordance with a partial response characteristic imposed on a time-related sequence of synchronous locations as in known in the art.
Various types of PRML recording are employed for various recording media. A type of PRML recording which is advantageously employed for magnetic recording media is Class IV PRML recording which employs a plurality of intermediate synchronous sample points for each transition location. The intermediate synchronous sample points are called synchronous write clock boundaries. Thus, the encoded data is recorded on a track as a sequence of variably spaced transitions having a particular relationship to the write clock boundaries.
The reproduction of the data as sensed at the readback transducer therefore requires that the readback signals be detected at the synchronous write clock boundaries. The maximum likelihood detection and decoding may then be conducted to recreate the original data. Ideally, the read channel waveform, when detected at the synchronous write clock boundaries, provides integer-type relationships to one another. Examples are −2, −1, 0, 1 and 2 for EPR4 (Extended Partial Response Class IV), and −1, 0 and 1 for PR4 (Partial Response Class IV).
PRML recording provides an excellent signal to noise characteristic and low error rate as compared to conventional peak detection of run length limited codes, therefore allowing the recording of data at higher recording densities. High density recording provides many advantages, such as higher capacity for the same types of data recording media.
Ideally, the track is moved past a readback transducer at a fixed speed, and the write clock boundaries are presented at a regular rate so that the recorded signals are appropriately aligned and spaced to allow generation by the readback transducer of equal and appropriately spaced electrical pulses for detection at the synchronous write clock boundaries by a sample clock for an ML detection channel.
Magnetic disk drives operate at fixed rotational speeds with the data recorded in a series of concentric tracks. Thus, the track velocity is relatively constant and the recorded signals are presented to the read channel at a regular rate, so that the sample clock provides samples at the write clock boundaries with only minor adjustments to the sample clock by a PLL (phase-locked-loop). This allows the ML detection channel to work optimally.
Conventional magnetic tape employs peak detection for decoding the data, rather than PRML. A difficulty of employing PRML with magnetic tape is that tape speeds are highly variable. Many magnetic tape drives access specific sections of the tape, possibly by stopping and reversing direction. For example, such magnetic tape drives may have a nominal velocity of 2 m/s and an acceleration rate of 2,000 m/s
2
. Also, the tape is simultaneously unwrapped from a supply reel, whose wrap radius is constantly being reduced, and wrapped onto a take up reel, whose wrap radius is constantly increasing, requiring that the reel motors constantly change speeds to produce approximately the same velocity across the readback transducer. Further, the tape does not always move across the readback transducer in a perfectly straight path, and may wander from side to side. Thus, the resultant velocity variations may be up to 15%.
Additionally, magnetic tape typically comprises a plurality of parallel tracks which are recorded and are read simultaneously. Thus, digital sample clocks may be employed and use global frequency averaging to control the clock timing, i.e., average the clocks across all the tracks. The digital clocks operate at a fixed frequency with a digital PLL to identify the transitions and maintain a phase lock on the input readback signal.
Typically, the read channel is sampled at a higher rate than the write clock rate. For example, the read sample clock operates at 1.25 times the write clock rate. In a digital channel, the read clock is generated by a fixed oscillator independently from the waveform that is being read from the tape. The PLL operates using this fixed oscillator to determine where the write clock boundaries occurred. The PLL does so without affecting the sample clock rate. Instead, it mathematically tracks the waveform that is being read from the tape.
Thus, the fixed samples are asynchronous and are independent from the synchronous write clock boundaries of the input signal, and present a highly variable relationship. No synchronous samples are therefore provided that could be used by an ML detector.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous interface for an asynchronous channel, the synchronous interface presenting estimated synchronous samples at estimated write clock boundaries.
Disclosed is a synchronous interface for an asynchronous channel, the channel providing asynchronous samples of an input signal, the input signal having synchronous write clock boundaries. A phase estimator is coupled to the asynchronous channel for estimating the timing offset of the input signal synchronous write clock boundaries from the asynchronous samples. A sample estimator is coupled to the asynchronous channel and to the phase estimator for estimating, from two sequential asynchronous samples bounding an input signal synchronous write clock boundary, the input signal amplitudes at the estimated timing offset from the asynchronous samples. Thus, the estimated input signal amplitudes are substantially synchronized with the input signal synchronous write clock boundaries.
The phase estimate is preferably accomplished by interpolating between sequential asynchronous sample clocks for determining the estimated timing offset of the input signal synchronous write clock boundaries.
The sample estimate is preferably accomplished by interpolating the amplitude of the input signal between two sequential asynchronous samples, at the estimated timing offset from the asynchronous samples.
Additionally, in a digital synchronous interface, a digital midpoint estimator estimates the midpoint between two sequential asynchronous digital samples, and a digital sample interpolator interpolates the amplitude of the input signal between the midpoint and the one of the two sequential asynchronous digital samples closest to the estimated timing offset.
The invention is primarily intended for a maximum likelihood detection channel for the detection of recorded magnetic PRML signals, the channel having a sample detector providing asynchronous digital samples of the signals. The method of the present invention estimates the offset of the input signal synchronous write clock boundaries from the timing of the sequential asynchronous samples, and estimates, from two sequential asynchronous samples, the input signal bounded thereby at the estimated synchronous timing write
Bocure Tesfaldet
Holcombe John H.
International Business Machines - Corporation
Sullivan Robert M.
LandOfFree
Synchronous interface for asynchronous data detection channels does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous interface for asynchronous data detection channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous interface for asynchronous data detection channels will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2462288