Synchronous integrated memory

Details Synchronous integrated memory Synchronous integrated memory

2000-07-24

2001-07-10

Mai, Son (Department: 2818)

Static information storage and retrieval

Magnetic bubbles

Guide structure

C365S189050, C365S221000, C365S233100

Reexamination Certificate

active

06259652

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the field of integrated technology. More specifically, the invention relates to a synchronous integrated memory in which data to be read out are output at a data output synchronously with an external clock signal.
In some synchronous memories, for example in DDR (Double Data Rate) SDRAMs (Synchronous Dynamic Random Access Memories), two data bits are read simultaneously from the memory cells, which have to be output successively at the same data output, namely with a positive and a negative edge of an external clock signal fed to the memory. In memories of this type, it can happen that a number of pairs of simultaneously read data bits firstly have to be buffer-stored before they can be output successively at the data output.
2. Summary of the Invention
The object of the invention is to provide a synchronous integrated memory which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which the buffer storage of the simultaneously read data pairs and the sequential outputting of the individual data bits with the different edges of the external clock signal are achieved in a favorable manner.
With the above and other objects in view there is provided, in accordance with the invention, a synchronous integrated memory, comprising:
memory cells;
a FIFO memory connected to the memory cells, the FIFO memory having at least two memory stages each for simultaneously buffer-storing two data items read from the memory cells;
each of the memory stages having a first output for outputting a respective buffer-stored first data item and a second output for simultaneously outputting a respective buffer-stored second data item;
a first output unit having an input connected to the first output of each of the memory stages of the FIFO memory and a data output outputting the first data item respectively received from the memory stages in dependence on a first clock signal; and
a second output unit having an input connected to the second output of each of the memory stages of the FIFO memory, a register for buffer-storing the second data item respectively received from the FIFO memory, and a data output for subsequently outputting the second data item in dependence on a second clock signal.
In other words, a First-In-First-Out (FIFO) memory is provided for buffer-storing the data read from the memory cells. This is a memory from which the buffer-stored data are read out in the same order in which they were written in. In each memory stage of the FIFO memory, the two data items that are respectively read simultaneously are written in simultaneously and read out again simultaneously at a later point in time. The synchronization of the first datum with the first clock signal is effected by the first output unit. Synchronization of the outputting of the second datum with the second clock signal is effected by means of the second output unit. The two output units are thus used for outputting the first and second data from all the stages of the FIFO memory. Since the synchronization with the two clock signals is only effected by the output units, but the first and second data are in each case output simultaneously from the memory stage of the FIFO memory, the FIFO memory can be constructed very simply. This is because, owing to the simultaneous outputting of the first and second data, only one output control signal is necessary for each memory stage, which signal controls the outputting of both respectively buffer-stored data items.
In accordance with a concomitant feature of the invention, the first clock signal drives the first output unit such that the first output unit outputs the first data item at the data output synchronously with a first type of edge of an external clock signal; and the second clock signal drives the second output unit such that the second output unit outputs the second data item at the data output synchronously with a second type of edge of the external clock signal. In other words, the first and second clock signals are inverse of each other.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an synchronous integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 5416745 (1995-05-01), Kawashima
patent: 5625594 (1997-04-01), Choi et al.
patent: 6147926 (2000-11-01), Park
patent: 6163501 (2000-12-01), Ohshima et al.

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