Synchronous frequency encoding technique for clock timing recove

Details Synchronous frequency encoding technique for clock timing recove Synchronous frequency encoding technique for clock timing recove

1989-09-07

1990-10-02

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, 3701001, H04J 306

Patent

active

049611887

ABSTRACT:
A sychronous frequency encoding technique (SFET) provides method and apparatus for recovering the timing of an isochronous source node input service signal at the destination node of a synchronous ATM telecommunication network despite cell jitter which arises from the broadband multiplexing and switching delays in the network. A source node control clock is employed which is of greater frequency than that of the service signal and as a result a data under-flow condition occurs in the cell assembly process at a rate that is a function of the difference between such clock frequencies. Regular cell transmission is inhibited for a period at each under-flow occurrence and this pseudo-"stuffed cell" gap is signaled by setting a flag bit carried by an ensuing transmitted cell. At the destination node, a timing stream from the control clock, which is synchronous with that of the source node, is regularly gapped by inserting periods of delay according to the ratio of flagged cells in the service transmission, thereby reducing the timing stream by the noted frequency difference and reproducing the original service signal frequency.

REFERENCES:
patent: 4530091 (1985-07-01), Crockett
"Adaptive Clock Synchronization Schemes for Real-Time Traffic in Broadband Packet Networks," R. P. Singh et al., 8th European Conference on Electrotechnics, Stockholm, Sweden, Jun. 1988.
"Jitter and Clock Recovery for Perodic Traffic in Broadband Packet Networks," R. P. Singh et al., IEEE Globecom '88, Florida, Dec. 1988.

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