Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
1999-07-15
2001-06-19
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S115000
Reexamination Certificate
active
06249157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous frequency dividing circuits and more particularly to a synchronous frequency dividing circuit for outputting frequency-divided signals in synchronization with a clock signal.
2. Description of the Background Art
The circuitry formed of connected multiple stages of delay type flip-flop circuits DFF
01
-DFF
03
of which outputs are fed back to the inputs as shown in
FIG. 23
is a typical frequency dividing circuit. Since flip-flop circuits DFF
01
-DFF
03
each cause delay, signals f/
2
, f/
4
, f/
8
which are divided by the circuits are delayed from a rise of a clock signal f by delays d
1
-d
3
as shown in FIG.
24
. Since divided signals f/
2
, f/
4
, f/
8
drive different loads, delays d
1
-d
3
are different from one another. Further, delays d
1
-d
3
are varied according to an operating frequency and the logical state of a load. When a logic circuit is formed by utilizing clock signal f and divided signals f/
2
, f/
4
, f/
8
, a circuit for adjusting delays d
1
-d
3
becomes complicated.
As a result, the number of transistors increases, which also increases power consumption.
In order to solve such problems, Japanese Patent Laying-Open No. 5-136691 discloses the frequency dividing circuit for latching divided signals f/
2
, f/
4
, f/
8
by flip-flops DFF
011
-DFF
013
and outputting divided signals f/
2
, f
14
, f/
8
in synchronization with clock signal f as shown in FIG.
25
.
In the frequency dividing circuit as shown in
FIG. 25
, however, divided signals f/
2
, f/
4
, f/
8
are synchronized with clock signal f, exactly with a delay of time d
4
, as shown in FIG.
26
. Further, divided signals f/
2
, f/
4
, f/
8
are not in phase with one another.
SUMMARY OF THE INVENTION
The present invention was made to solve the problems above and its object is to provide a frequency dividing circuit for synchronizing divided signals with a clock signal without delay. Another object of the present invention is to provide a frequency dividing circuit in which divided signals are in phase with one another.
A frequency dividing circuit according to one aspect of the present invention includes a flip-flop circuit, a latch circuit, and a delay circuit. The flip-flop circuit divides a clock signal. The latch circuit latches a signal divided by the flip-flop circuit and outputs the signal in synchronization with the clock signal. The delay circuit delays the clock signal and outputs the clock signal in synchronization with the signal from the latch circuit.
In the frequency dividing circuit, delay is caused from the time when the latch circuit receives the clock signal to the time when the latch circuit outputs the signal divided by the flip-flop circuit. That is, the signal output from the latch circuit is in synchronization with the clock signal with a delay of prescribed time. The delay circuit delays the clock signal by the prescribed time for latch circuit delay. Thus, the clock signal delayed by the delay circuit and the signal divided by the flip-flop circuit are in synchronization with each other without delay.
A frequency dividing circuit according to another aspect of the present invention includes a first flip-flop circuit, a first latch circuit, a second flip-flop circuit, a third flip-flop circuit, and a second latch circuit. The first flip-flop circuit divides a clock signal. The first latch circuit latches a signal divided by the first flip-flop circuit and outputs the signal in synchronization with the clock signal. The second flip-flop circuit divides the signal from the first latch circuit. The third flip-flop circuit receives the signal from the second flip-flop circuit and outputs the signal in phase with the signal divided by the first flip-flop circuit. The second latch circuit latches the signal from the third flip-flop circuit and outputs the signal in synchronization with the clock signal.
In the frequency dividing circuit, the signal from the first flip-flop circuit is in phase with the signal from the third flip-flop circuit. The signals from the first and third flip-flop circuits are output in synchronization with the clock signal by the first and second latch circuits. Thus, the signals divided by the first and second flip-flop circuits are output in phase with each other.
A frequency dividing circuit according to still another aspect of the present invention includes a first flip-flop circuit, a first latch circuit, a second flip-flop circuit, and a second latch circuit. The first flip-flop circuit divides a clock signal. The first latch circuit latches a signal divided by the first flip-flop circuit and outputs the signal in synchronization with the clock signal. The second flip-flop circuit divides the signal from the first latch circuit. The second latch circuit latches the signal from the second flip-flop circuit and outputs the signal in synchronization with the signal from the first latch circuit.
In the frequency dividing circuit, the signal from the second latch circuit is synchronized with the signal from the first latch circuit. This is because the signal from the second flip-flop circuit has a lower frequency than the clock signal and therefore it does not always have to be synchronized with the clock signal. Accordingly, by using the signal from the first latch circuit to operate the second latch circuit, power consumption can be reduced as compared with a case where the clock signal is used.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4656649 (1987-04-01), Takahashi
patent: 4816700 (1989-03-01), Imel
patent: 5341031 (1994-08-01), Kinoshita et al.
patent: 5-136691 (1993-06-01), None
Nakura Toru
Ueda Kimio
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Linh
Tran Toan
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