Synchronous frequency dividers and components therefor

Electrical pulse counters – pulse dividers – or shift registers: c – Pulse counting or dividing chains – Ring or reversible counter

Reexamination Certificate

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C327S117000, C327S202000

Reexamination Certificate

active

11343234

ABSTRACT:
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a “1”, and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.

REFERENCES:
patent: 4258273 (1981-03-01), Straznicky et al.
patent: 4656649 (1987-04-01), Takahashi
patent: 5714896 (1998-02-01), Nakagawa et al.
patent: 5719798 (1998-02-01), Lutz et al.
patent: 0 473 251 (1992-03-01), None
T. Mathew et al; 2-Bit Adder Carry and Sum Logic Circuits Clocking at 19 GHz Clock Frequency in Transfered Substrate HBT Technology; Conference Proceedings; 2001 International Conference on Indium Phosphide and Related Materials; IPRM; Nara, Japan; May 14-18, 2001;International Conference on Indium Phosphide and Related Materials; New York, New York; IEEE; US; vol. conf. 13; May 14, 2001; pp. 505-508; XP010547086.
A. J. Acosta et al; Design and Characterization of a CMOS VLSI Self-Timed Multiplier Architecture Based on a Bit-Level Pipelined-Array Structure; IEE Proceedings:Circuits Devices and Systems; Institution of Electrical Engineers; Stenvenage, GB; vol. 145; No. 4; Aug. 5, 1998; pp. 247-253; XP006010781; ISSN:1350-2409.

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