Synchronous flash memory command sequence

Details Synchronous flash memory command sequence Synchronous flash memory command sequence

2007-01-09

2007-01-09

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S233100, C365S193000, C365S203000, C365S189011

Reexamination Certificate

active

10877576

ABSTRACT:
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

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