Synchronous FIFO having an alterable buffer store

Details Synchronous FIFO having an alterable buffer store Synchronous FIFO having an alterable buffer store

1993-10-05

1995-04-11

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 582, 370 859, 370 8513, 36518901, 36518904, 36518908, H04Q 1104

Patent

active

054065542

ABSTRACT:
A synchronous first-in, first-out ("FIFO") having an alterable buffer store includes a dual-ported, random access memory ("RAM") based memory device incorporating conventional "empty" and "full" flags while also providing an alternate mode of operation in which the inhibiting effects of the "empty" and "full" flags are disabled whereby information contained within the FIFO may be modified before being read out. The alternate mode of operation is particularly useful in asynchronous transfer mode ("ATM") networking applications.

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