Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-03-27
2001-05-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C365S230090
Reexamination Certificate
active
06240047
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to an integrated circuit with four-bit data prefetch.
BACKGROUND OF THE INVENTION
Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology have greatly increased demand for high-speed under various modes of operation of these SDRAM circuits. These SDRAM circuits must provide wide data paths of at least 32-bits for typical memory systems. Data flow at each bit position of a 32-bit data word must function under existing 1-, 2-, 4-, and 8-bit serial and interleaved burst modes at high system clock frequencies. At these high clock frequencies, however, there is insufficient time for each data bit to flow from a sense amplifier in a memory array to an output terminal. For example, at a clock frequency of 300 MHz, one data bit is produced at each bit position every 3.33 Ns. Moreover, if the data rate is doubled, and a data bit is produced at each edge of the system clock, only 1.67 Ns is available for each data bit. By way of comparison, a typical read array time, or time for one data bit to flow from a sense amplifier to an output buffer, may be 5.3 Ns. A typical write array time, or time for one data bit to flow from an input buffer to a sense amplifier, may be 9.5 Ns. Current JEDEC specifications for pipeline and 2-bit prefetch operation help reduce the data rate problem but cannot meet future demands. Moreover, future architecture requirements must continue to function under existing SDRAM operational modes.
SUMMARY OF THE INVENTION
These problems are resolved by a memory circuit for operating synchronously with a system clock signal. The memory circuit has a memory array with a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits produces a select signal at a respective column select line in response to a first column address signal. A plurality of sense amplifier circuits is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line. A control terminal of each select transistor of a group of sense amplifier circuits is connected to a respective column select line. A data sequence circuit is coupled to receive four data bits from four respective data lines in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.
The present invention produces four data bits for each bit position in response to a single column address. The data bits are produced in a predetermined order in response to a plurality of system clock cycles.
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Kawamura J. Patrick
Koelling Jeffrey E.
Nelms David
Rountree Robert N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Yoha Connie C.
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