Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-12-20
2005-12-20
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189110, C365S193000, C365S189050
Reexamination Certificate
active
06977864
ABSTRACT:
A data output driver of a combination type of a synchronous dynamic random access memory (SDRAM) device operated in both of a single data rate (SDR) mode and a double data rate (DDR) mode, the data output driver includes a first input/output line connected between a drain of a pull-up transistor and a data input/output pad, a second input/output line connected between a drain of a pull-down transistor and the data input/output pad, at least one switching unit formed on each of the first input/output line and the second input/output line, and at least one resistor parallel-connected with the switch and formed on each of the first input/output line and the second input/output line, wherein the switching unit is turned on or turned off by selecting one of a SDR mode and a DDR mode.
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patent: 6426900 (2002-07-01), Maruyama et al.
patent: 6496403 (2002-12-01), Noda et al.
patent: 2004/0100837 (2004-05-01), Lee
patent: 1999-0066271 (1999-08-01), None
patent: 10 278653 (2000-10-01), None
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Nguyen Tuan T.
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