Static information storage and retrieval – Information masking
Reexamination Certificate
1999-10-25
2001-03-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Information masking
C365S230080, C365S230040
Reexamination Certificate
active
06205046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous dynamic random-access memory (hereinafter called SDRAM), and more particularly to a double data rate (DDR) SDRAM which masks input/output data signals to prevent data from being written into the memory.
2. Description of the Related Art
Conventionally, double data rate SDRAMs such as 128M-bit &mgr;PD45D128442, &mgr;PD45D128842, and &mgr;PD45D128164 have been made available from NEC Corporation. These SDRAMs are compatible with SSTL2 (Stub Series Terminal Logic for 2.5V).
FIG. 8
is a block diagram showing a conventional DDR SDRAM. This SDRAM comprises a clock generator
11
including a DLL (Delay-Lock Loop)
11
a
, a command decoder
12
, a mode register
13
, a control logic
14
, a row address buffer and refresh counter
15
, a column address buffer and burst counter
16
, a row decoder
17
, a memory cell array
18
composed of banks, a sense amplifier
19
, a column decoder
20
, a data control circuit
21
, a latch circuit
22
, a byte mask data latch circuit
23
b
, and an input/output buffer
24
.
In the SDRAM described above, the clock generator
11
receives the clock signal CLK, the active-low clock signal/CLK, the clock enable signal CKE, and so on and, at the same time, outputs the internal (first) clock signal. The DLL
11
a
receives the clock signal CLK and the active-low clock signal /CLK and, at the same time, outputs the delay (second) clock signal. The delay clock signal from the DLL
11
a
drives only the input/output buffer
24
provided in the SDRAM. The command decoder
12
receives the chip select signal /CS, the column address strobe signal /CAS, the row address strobe signal /RAS, and the write enable signal /WE and, at the same time, outputs various control signals to the control logic
14
.
The column address signals A
0
-A
11
and the bank selection signals BA
0
and BA
1
are sent to the mode register
13
, the row address buffer and refresh counter
15
, and the column address buffer and burst counter
16
, respectively. The data signal DQ and the data strobe signal DQS are input to, or output from, the input/output buffer
24
. In addition, the data mask signal DM is sent to a byte mask data latch circuit
23
b.
The byte mask data latch circuit
23
b
described above comprises two latch circuits,
31
and
33
, and an inverter
32
as shown in the block diagram in FIG.
9
. The data mask signal DM is sent to the latch circuits
31
and
33
from an external memory controller (not shown in the figure). The data strobe signal DQS is also sent to the latch circuits
31
and
33
. The byte mask data latch circuit
23
b
outputs the mask signals MASK
1
and MASK
2
. These mask signals MASK
1
and MASK
2
are signals that inhibit writing data into the internal memory to prevent data from being written into the memory cell array
18
.
As shown in
FIG. 10
, this SDRAM receives a write command on the rising edge of the clock signal CLK and, at the same time, receives the column address signals A
0
-A
8
(×8 device). Then, the data strobe signal DQS and the data signal DQ described above are sent to the SDRAM.
Unlike a single data rate SDRAM, this DDR SDRAM synchronizes with both the rising edge and the falling edge of the data strobe signal DQS to receive the data signal DQ to double the data rate. The data mask signal DM is latched by the latch circuits
31
and
33
in synchronization with both the rising edge and the falling edge of the data strobe signal DQS. The data mask signal DM, when high, masks the data signal to prevent data from being written into the memory cell array
18
.
The data strobe signal DQS latches the data mask signal DM on both the rising edge and the falling edge as described above. Therefore, the data mask signal DM is sent to both the latch circuits
31
and
33
of the byte mask data latch circuit
23
b
shown in FIG.
9
.
FIG. 10
is a timing diagram illustrating the operation of the SDRAM. The diagram in
FIG. 10
indicates that the data mask signal DM operates at the same frequency as that of the clock signal CLK and that the data signal DQ may be masked on a bit basis. In this case, the DDR SDRAM can operate twice as fast as a single data rate SDRAM.
As described above, the conventional SDRAM, which allows the data signal DQ to be masked on a bit basis, operates at a frequency twice as high as that of the single data rate SDRAM. However, this SDRAM requires rigorous setup times and hold times during data input, making it difficult to obtain even an enough system margin.
To solve this problem, consider an SDRAM such as the one shown in FIG.
11
. This SDRAM circuit receives an additional data mask signal DM
2
from an external memory controller (not shown in the figure), thus making it possible to use two separate data mask signals: one for use when the data strobe signal DQS rises and the other for use when the data strobe signal DQS falls.
FIG. 12
is a block diagram of a byte mask data latch circuit
23
c
included the SDRAM shown in FIG.
11
.
FIG. 13
is a timing diagram illustrating the operation of the byte mask data latch circuit
23
c
. The problem with the byte mask data latch circuit
23
c
is that it requires an additional pin for external connection because of two data mask signals, DM and DM
2
. Thus, it does not maintain compatibility with conventional products.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous dynamic random-access memory (SDRAM) which uses data mask signals to perform byte mask operation on a bit basis at a low frequency while maintaining compatibility with conventional SDRAMs and which provides enough margins not only for the DRAM but for the overall system.
The double data rate synchronous dynamic random-access memory according to the present invention uses unused column address signals for data mask signals for use when the data strobe signal rises and falls to mask data signals on a bit basis.
The double data rate synchronous dynamic random-access memory according to the present invention has a multiple-bank memory cell array driven in synchronization with a first clock, the synchronous dynamic random-access memory comprising an input/output buffer to or from which data signals of the synchronous dynamic random-access memory are input or output in response to a second clock synchronizing with the first clock; a latch circuit which performs an input/output of the data signals between the input/output buffer and the memory cell array; and a byte mask data latch circuit which allocates an unused column address signal to the latch circuit for use when the data strobe signal rises or falls for outputting a mask signal; wherein the mask signal write-masks the input/output of the latch circuit.
The configuration according to the present invention makes the synchronous dynamic random-access memory compatible with conventional products and, at the same time, masks data signals during byte mask operation at a low frequency on a bit basis.
According to the present invention, the setup time and the hold time during data input become long as in the single data rate operation, giving enough margins not only to the SDRAM but to the whole system. Furthermore, using an unused column address signal for masking data ensures compatibility with conventional products with no additional pin. In addition, on conventional products, the SSTL interface must be used to operate at the same frequency at which the clock signal CLK, active-low clock signal /CLK, data strobe signal DQS, and data signal DQ operate. On the other hand, the configuration according to the present invention eliminates the need for that interface, thus reducing the system current consumption.
REFERENCES:
patent: 5991232 (1999-11-01), Matsumura et al.
patent: 6067260 (2000-05-01), Ooishi et al.
Le Thong
NEC Corporation
Nelms David
Young & Thompson
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