Synchronous dynamic random access memory

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523001, 365193, 365221, G11C 800

Patent

active

055965415

ABSTRACT:
A synchronous DRAM has cell arrays arranged in a matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks are used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

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European Search Report, dated Mar. 8, 1986, Appl. No. 94115367.8.
Masao Taguchi, et al. "A 40-ns 64-Mb Dram with 64-b Parallel Data Bus Architecture", IEEE Journal of Solid-State Circuits, Nov. 26, 1991, No. 11, pp. 1493-1497.
European Search report, dated Nov. 16, 1995, Appl. No. 94115367.8.
Masao Taguchi, et al., "A 40-ns 64-Mb DRAM with 46-b Parallel Data Bus Architecture", IEEE Journal of Solid-State Circuits 26 (1991) Nov., No. 11 .

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