Synchronous dynamic random access memory

Details Synchronous dynamic random access memory Synchronous dynamic random access memory

1993-11-02

1994-08-16

Fears, Terrell W.

Static information storage and retrieval

Addressing

Multiplexing

36518902, 365233, G11C 1300

Patent

active

053392760

ABSTRACT:
A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.

REFERENCES:
patent: 4128900 (1978-12-01), Lappington
patent: 4661928 (1987-04-01), Yasuoka
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patent: 5083296 (1992-01-01), Hara et al.
patent: 5262991 (1993-11-01), Pope
IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, "Self-Timed Performance Test for Stand-Alone Random-Access Memories," pp. 161, 162.
IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan., 1989, pp. 47-49, "Method Providing Wait-State Processor Cycles Using Medium Speed Dynamic RAM".

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