Synchronous dynamic memory device capable of operating over wide

Details Synchronous dynamic memory device capable of operating over wide Synchronous dynamic memory device capable of operating over wide

1995-12-21

1998-05-19

Heckler, Thomas M.

395556, 395432, G06F 108

Patent

active

057548382

ABSTRACT:
In a synchronous DRAM, internal clock signals in synchronism with clock signals fed from an external unit are generated by a PLL circuit or a DLL circuit to eliminate signal delays. In order to provide a dynamic RAM that is capable of stably operating with clock signals over a wide range of frequencies; a change-over circuit is provided which changes the range of variable frequencies of the PLL circuit or changes the variable delay time of the DLL circuit based upon mode-setting information fed from an external unit.

REFERENCES:
patent: 4239991 (1980-12-01), Hong et al.
patent: 4644184 (1987-02-01), Miyawaki et al.
patent: 4985868 (1991-01-01), Nakano et al.
patent: 5623638 (1997-04-01), Andrade
"HM5216800, HM5416800 Series Data Book" published by Hitachi, Ltd., Jan. 18, 1993, pp. 1-36.

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