Synchronous DRAM having initial mode setting circuit

Details Synchronous DRAM having initial mode setting circuit Synchronous DRAM having initial mode setting circuit

1994-09-19

1995-09-05

Yoo, Do H.

Static information storage and retrieval

Addressing

Sync/clocking

3652257, 36523006, G11C 1300

Patent

active

054485282

ABSTRACT:
The initial mode setting circuit 30 has a circuit 31 for generating a reset pulse RST after detecting that the power source voltage VCC has reached a specified value when the power source voltage VCC starts up, and fuses 32 to 37, each one end of which is commonly connected to the output end of the reset signal generating circuit 31 and the other ends of which are connected to one of either the set input end S or the reset input end R of the flip flops 11 to 13. The fuses 32 to 37 are melted and cut off electrically or with a laser.

REFERENCES:
patent: 5311483 (1994-05-01), Takasugi

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