Synchronous DRAM having a high data transfer rate

Details Synchronous DRAM having a high data transfer rate Synchronous DRAM having a high data transfer rate

1998-08-25

1999-09-14

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36518909, 36523003, G11C 800

Patent

active

059532866

ABSTRACT:
In a semiconductor memory including a plurality of synchronous DRAMs controlled by one common memory controller, each of the synchronous DRAMs has first and second terminals for receiving a reference clock supplied from the memory controller. A signal line for this reference clock is laid out in such a manner that the signal line is connected from the memory controller firstly to the first terminal of the most remote synchronous DRAM, and then, to respective first terminals of the remaining synchronous DRAMs, in order, towards the nearest synchronous DRAM and further, to the second terminal of the nearest synchronous DRAM, and then, to respective second terminals of the remaining synchronous DRAMs, in order, towards the most remote synchronous DRAM. Thus, on the basis of the difference in phase between the same reference clock applied to the first and second terminals, each of synchronous DRAMs can obtain a delay information of the same synchronous DRAM attributable to the location of the same synchronous DRAM from the memory controller, and therefore, can set an optimum read-out data outputting timing, so that the setup time and the hold time for the read-out data supplied from all the synchronous DRAMs can be ensured. Thus, the reading operation can be speeded up by elevating the clock frequency.

REFERENCES:
patent: 5384738 (1995-01-01), Miyaoka et al.
patent: 5646904 (1997-07-01), Ohno et al.
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 5881016 (1999-03-01), Kenkare et al.

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