Image analysis – Image transformation or preprocessing – Changing the image coordinates
Reexamination Certificate
1999-01-27
2002-04-23
Johnson, Timothy M. (Department: 2623)
Image analysis
Image transformation or preprocessing
Changing the image coordinates
C348S567000, C348S581000, C382S305000
Reexamination Certificate
active
06377713
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for downsizing a digital video image, such as an image corresponding to the MPEG-2 standard. The invention is particularly suitable for providing a reduced image for a picture-in-picture mode on a television.
The transmission of digital video data via broadband communication systems such as cable television or satellite television networks has become increasingly popular. Digital decoders, e.g. set-top boxes, are provided in consumers' homes for use in receiving the digital video signals and processing the signals in a format that is suitable for display on a television, video display terminal, or the like. However, the processing and memory storage requirements of such set-top boxes is significant and must be kept as low as possible in order to maintain the commercial feasibility of the network.
In particular, in many cases it is desirable to provide a capability for converting a full size digital video image, e.g., 720×480 (NTSC) or 720×576 (PAL) pixels, to a smaller display image. This feature is required for applications such as picture-in-picture mode, where the downsized image from one program is displayed as an overlay to the image from a second program, or for a program guide display mode, where a reduced display image is provided alongside a program schedule, menu or the like.
However, conventional configurations do not allow for image downsizing since there is no additional memory space available to store averaged pixel values. Generally, with the complexity for performing MPEG video decompression and full sized display, there is no Dynamic Random Access Memory (DRAM) bandwidth available to perform additional display downsizing, e.g., using a 54 MHz Synchronous DRAM (SDRAM), and a sixteen bit wide data bus. This bandwidth problem can be addressed theoretically, e.g., by increasing the SDRAM speed from 54 MHz to 81 MHz or higher. However, this can wreak havoc on the system due to the higher speed congestion of the SDRAM data bus, the additional cost of the required premium memory part, and the general difficulty of high speed design.
Accordingly, it would be desirable to provide a method and apparatus for display downsizing which can be implemented without additional processing speed or memory usage requirements. The system should have the capability to provide a full sized, upsized, or a downsized image as required. The system should be compatible with MPEG-2 or other digital video standards. In a particular embodiment, the system should provide an architecture and methodology which uses only a 16 Mbit SDRAM at 54 MHz, and a 16-bit wide data bus.
The system should take advantage of an existing on-chip memory such as a line buffer or register file which is otherwise not used during downsizing.
The system should be compatible with field mode (e.g., interlaced scan) and frame mode (e.g., progressive scan) video.
The present invention provides a system having the above and other advantages.
SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus for downsizing a digital video image, such as an image corresponding to the MPEG-2 standard.
A method for processing digital video data to display a downsized image thereof, includes the steps of: decompressing compressed digital video pixel data that is received from a channel to provide pixel data of an original image; averaging horizontally adjacent pixel pairs of at least a portion of the original image to provide horizontally downsized pixel data; storing the horizontally downsized pixel data in a first bank of a memory; and storing data from every other pixel of the at least a portion of the original image in a second bank of the memory. A two-tap filter may be used to average the horizontally adjacent pixel pairs.
The memory may be a dual-bank or other multi-bank memory, for example.
A horizontally and vertically downsized image can be obtained by retrieving the horizontally downsized pixel data, and averaging the corresponding vertically adjacent data from every other pixel just prior to display. The vertical averaging can be achieved by providing the horizontally downsized pixel data from the first bank to a line buffer, pixel-by-pixel. The line buffer should be sized to store at least the pixels from one line of the horizontally downsized pixel data, plus one pixel. With this arrangement, successive vertically adjacent pixel pairs will be available in the line buffer for output to, and averaging by, an averaging circuit. The pixel pair is averaged just prior to display.
Moreover, pixel data of the original image can be recovered by retrieving both the horizontally downsized pixel data and the data from every other pixel, and performing simple arithmetic calculations. Specifically, a difference is calculated between (a) twice a value of the respective retrieved portions, and (b) a value of the respective retrieved corresponding portions, to recover pixel data corresponding to the original image. It is desirable to recover pixel data corresponding to the original image for decompressing predictive-coded images.
The method includes the further steps of: retrieving vertically adjacent lines of the horizontally downsized pixel data from the first bank; and averaging the lines to provide vertically and horizontally downsized pixel data for display. For example, a two-tap filter may be used to average the pixel data in the vertically adjacent lines.
The method includes the further steps of: retrieving portions of the horizontally downsized pixel data from the first bank; retrieving corresponding portions of the data from every other pixel from the second bank; and processing the retrieved portions and the retrieved corresponding portions to recover pixel data of the original image. This may be achieved using adder circuitry.
The method includes the further step of: providing the recovered pixel data of the original image for use in the decompressing step. For example, the recovered pixel data may represent a past or future image used for temporal (e.g., inter-frame) prediction of the current, original image. In this case, the recovered pixel data is required for motion compensation and/or estimation. This step is not needed if the current, original image is an intra-frame coded image.
Additionally, B-picture data is not used as a reference picture for motion compensation and/or estimation, so, for this type of data, it is sufficient to store only the horizontally averaged pixel data but not the data from every other pixel of the original image. For I- and P-pictures, both the horizontally averaged pixel data and the data from every other pixel of the original image should be stored.
The memory may be an SDRAM, for example, although the invention may be used with virtually any type of multi-bank memory which is available presently or in the future.
Furthermore, the storing of the horizontally downsized pixel data and the data from every other pixel should occur no later than after one-half of the original image has been decoded to avoid having the decoding catch up to the displaying of the pixel data, in which case the display of data is impaired.
For field mode video, pixel data from each field is processed separately.
A corresponding apparatus is presented.
REFERENCES:
patent: 5315388 (1994-05-01), Shen et al.
patent: 5386212 (1995-01-01), Shen et al.
patent: 5638128 (1997-06-01), Hoogenboom et al.
patent: 5675387 (1997-10-01), Hoogenboom et al.
patent: 5844541 (1998-12-01), Cahill, III
General Instrument Corporation
Johnson Timothy M.
Lipsitz Barry R.
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