Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1996-12-03
2001-02-13
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S506000
Reexamination Certificate
active
06188685
ABSTRACT:
TECHNICAL FIELD
The invention a a transmission system for digital signals which are combined into a multiplex signal in which the digital signals are inserted in the form of bytes into frames of an established frame format, where each frame has areas for control data and areas for payload data, in which several network elements that are interconnected by transmission media are located, each comprising an adapter circuit to balance phase variations in an incoming multiplex signal, and where the adapter circuit has a buffer memory for payload data bytes, a write address generator which controls the buffer memory in a way so that a number of payload data bytes are stored within a write cycle, and has a read address generator which controls the buffer memory in a way so that a number of payload data bytes are read within a read cycle. The invention is also directed to a network element for such a transmission system.
BACKGROUND OF THE INVENTION
A transmission system for digital signals which are combined into a multiplex signal is e.g. a transmission system for the synchronous digital hierarchy, or a transmission system for synchronous optical networks conforming to the SONET standard, which the American National Standards Institute has adopted. In a transmission system for the synchronous digital hierarchy (SDH), and in a transmission system conforming to the SONET standard, signals to be transmitted are combined into a multiplex signal and are structured in frame form. Such a frame is called a synchronous transport module STM in the SDH; it is described e.g. in the CCITT recommendations G.707, G.708 and G.709. The frame comprises 270 columns and 9 lines. Each column of a line contains one byte: the columns 1 to 9 in lines 1 to 3 and 5 to 9 each have the so-called Section Overhead (SOH) for control and error detection information. Column 1 to 9 in the fourth line has a pointer-managing unit which is designated an AU-Pointer (AU-P). The payload information, the “STM-1 Payload” is stored in the remaining columns and lines. An “STM-1 Payload” is e.g. stored in a virtual container VC-
4
, which contains an area for payload data and an area for control data (path overhead POH).
Further units established in SDH are e.g. administrative units, e.g. AU-
4
, which are composed of a virtual container VC and an AU-Pointer, and tributary units, e.g. TU-
12
, which are composed of a virtual container and a TU-Pointer.
STM signals are emitted via a transmission path containing circuits at predetermined intervals, e.g. at network elements, in which an incoming STM-1 signal is adapted to a local (internal) standardized clock pulse of the network element. These circuits perform clock pulse adaptations and balance the phase variations by means of a known byte-stuffing method. When required in this case, stuffing bytes are inserted at predetermined places in the frame (bytes H1, H2, H3) (CCITT recommendation G.709). The payload data are omitted from the stuffing place with a positive stuffing procedure, and payload data are inserted into the stuffing place with a negative stuffing procedure. A stuffing procedure is also called a pointer action, since the value of the pointer must be changed after each stuffing procedure; the pointer then points to a different payload data byte.
An investigation of these pointer actions with the model of an SDH transmission system is known from: Henry L. Owen and Thomas M. Klett “Synchronous digital hierarchy network pointer simulation”, Computer Networks and ISDN Systems 26, 1994, pages 481 to 491. The model illustrated in
FIG. 3
therein comprises a number of network elements
1
, . . . ,N−1. In network element
1
, signals (telephone, video, computer data) are supplied to the network and combined into SDH signals in a mapper (synchronizer). An internal clock pulse is assigned to each network element N.
FIG. 5
therein illustrates a model of a network element N. A flexible memory (first-in, first-out, FIFO) serially receives frames of an input signal with the clock pulse of the preceding network element N−1. The bytes are written to the memory with this clock pulse, and the bytes are read from the memory with the clock pulse of network element N. Whether a byte is written to the memory depends on whether it is a payload data byte or an overhead byte. This takes place through a byte presenter illustrated in
FIG. 5
, which is controlled by the clock pulse of the preceding network element N−1. In the case of an AU-
4
, all payload data bytes are written to the same memory and other cases have different memories for different kinds of payload data. The number of bytes in the memory determines when the memory is too full or too empty. Pointer actions are triggered by a defined upper and lower threshold value, which is controlled by a stuffing device (pointer request generator, pointer processor). Disturbing effects can occur with these pointer actions, which cause phase variations at the receiving place (desynchronizer). These effects are described e.g. in: Henry L. Owen and Peter E. Sholander “Methodology and Results of Synchronous Digital Hierarchy Network Payload Jitter Simulation” SIMULATION, January 1995, pages 1 to 8. These effects occur when a network node is in a standby (holdover) condition following the failure of an external synchronization source, and a stuffing device derives the pointer actions as a function of the fill level of a memory with fixed threshold values. Clock pulse differences of up to +/−4.6 ppm can take place during the standby condition.
SUMMARY OF THE INVENTION
The invention has the task of introducing a transmission system for digital signals that are combined into a multiplex signal, in which the mentioned disturbing effects no longer occur. Such a transmission system is for digital signals that are combined into a multiplex signal, in which the digital signals are inserted in the form of bytes into frames of an established frame format, where each frame has areas for control data and areas for payload data, in which several network elements that are interconnected by transmission media are located, each comprising an adapter circuit to balance phase variations in an incoming multiplex signal, and where the adapter circuit has a buffer memory for payload data bytes, a write address generator which controls the buffer memory in a way so that a number of payload data bytes are stored within a write cycle, and has a read address generator which controls the buffer memory in a way so that a number of payload data bytes are read within a read cycle, characterized in that the read address generator is controlled so that the number of payload data bytes read within the read cycle is less than the number of payload data bytes stored within a write cycle, and in that each network element has a sort facility which sorts the payload data bytes so that a multiplex signal transmitted by a network element has the established frame format. The invention has the additional task of introducing a network element for such a transmission system. It is thus a network element of a transmission system for digital signals that are combined into a multiplex signal, which are inserted in the form of bytes into frames of an established frame format, where each frame has areas for control data and areas for payload data, with an adapter circuit for balancing phase variations in a multiplex signal which can be supplied to the network element, having a buffer memory for payload data bytes, a write address generator which controls the buffer memory in a way so that a number of payload data bytes are stored within a write cycle, and a read address generator which controls the buffer memory in a way so that a number of payload data bytes are read within a read cycle, characterized in that the read address generator is controlled so that the number of payload data bytes read within the read cycle is less than the number of payload data bytes stored within a write cycle, and in that the network element has a sort facility which sorts the r
Dive Geoffrey
Kasper Jürgen
Wolf Michael
Alcatel
Boakye Alexander
Nguyen Chau
Ware Fressola Van der Sluys & Adolphson LLP
LandOfFree
Synchronous digital transmission system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous digital transmission system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous digital transmission system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2577478