Synchronous digital data transmission interface

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S362000

Reexamination Certificate

active

08009783

ABSTRACT:
The field of the invention is that of transmission interfaces for synchronous digital input signals composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency. The interface according to the invention comprises at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel. The output samples are transmitted at a second clock frequency, integer multiple N of a third frequency. The third frequency is substantially equal to the first frequency. Each sampled bit is substantially composed of N samples. The interface has an electronic device for frequency-locking the third frequency onto the first clock frequency. The device has means for counting the number of samples composing each sampled bit. The device also has incrementation-decrementation means for the third clock frequency configured in such a manner that the third clock frequency is increased when the number of samples is less than the integer multiple N and decreases when the number of samples is greater than N.

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patent: 6271697 (2001-08-01), Hayashi et al.
patent: 2004/0090277 (2004-05-01), Tsyrganovich
patent: 2005/0134337 (2005-06-01), Lee et al.
patent: 2007/0222648 (2007-09-01), Sontag et al.
patent: 0397198 (1990-11-01), None
Widmer A. X. et al.: “Single-Chip 4 X 500-MBD CMOS Transceiver” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 31, No. 12, (Dec. 1, 1996), pp. 2004-2013, XP000691821; ISSN: 0018-9200.

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