Synchronous detector

Details Synchronous detector Synchronous detector

1999-11-12

2003-01-07

Nguyen, Lee (Department: 2683)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S142000, C370S335000

Reexamination Certificate

active

06504883

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a mobile radio communication apparatus, and more specifically, it relates to a synchronous detector used in a code division multiple access (CDMA) radio communication receiver.
2. Description of the Background Art
A synchronous detector used in a code division multiple access (CDMA) receiver, for example, is described in a paper entitled “A Development Conditions and Its Technical Issue of Digital Matched Filters in Spread-Spectrum Communication Systems,” Hisao Tachika, The Institute of Electronics, Information and Communication Engineers, SST92-21 (1992). In the CDMA receiver, transmission data is spread and de-spread by using the same pseudo-noise (PN) code between a transmitting station and a receiving station as a spread code. The PN code is a bit sequence consisting of logical values [+1] or [−1]. A time interval between two bits is referred to as a chip. A correlation value between two PN codes is obtained by multiplying each bit of the two PN codes for every chip and then summing the results of the multiplication. Consequently, if the phases of the PN codes match, the correlation value becomes large. On the other hand, if the phases of the two PN codes do not match, the correlation value becomes almost zero. When the CDMA receiver receives a radio signal, the CDMA receiver needs to match the phase of the PN code of the radio signal and the phase of a local PN code generated by the CDMA receiver in order to spread-spectrum demodulate the radio signal. Matching the phases of the two PN codes is referred to as synchronous acquisition.
The radio signal received at an antenna is demodulated to baseband signals consisting of an inphase baseband signal (I signal) and a quadrature baseband signal (Q signal) by multiplying, respectively, an inphase oscillation signal and a quadrature oscillation signal generated by a local oscillator.
To acquire synchronization of the radio signal, first, an inphase correlation value is calculated by multiplying each bit of the PN code of the inphase baseband signal with each bit of the local PN code and then summing the results of the multiplication. Second, a quadrature correlation value is determined in a similar way. To obtain a correlation power of the received signal, the inphase correlation value and the quadrature correlation value are each squared and then the squared results are added to each other.
The calculations of the correlation power are performed to all phases of the PN code of the radio signal by shifting 1 chip or ½ chip or ⅓ chip to detect at least one synchronous phase (or synchronous timing). Accordingly, the synchronous phase of the PN code of the radio signal to the local PN code can be acquired based on detecting the timing having the highest correlation power or the timing having a higher correlation power greater than a predetermined threshold. In general, a digital matched filter performs the calculations described above. That is, the digital matched filter calculates the correlation powers to all phases of the received signal by shifting 1 chip or ½ chip or ⅓ chip. Thus, at least one synchronous phase having the highest correlation power or the higher correlation power beyond a predetermined threshold can be detected.
In a conventional CDMA communication system, a pilot signal is used to acquire the synchronization of the received signal. Since the pilot signal is comprised of a predetermined bit sequence, e.g., all bits are logical value [+1] or [−1], the pilot signal is a PN code that does not modulate. Thus, it is possible for the CDMA receiver to calculate the correlation power at ½ chip rate or {fraction (
1
/
3
)} chip rate to obtain a higher correlation power rather than that of 1 chip rate.
The digital matched filter stores the received signal corresponding to the number of the chip in corresponding registers, and multiplies each bit of the received signal with each bit of the local PN code for every chip. When the next bit of the radio signal is input, each bit stored in the register is shifted, and the next correlation power of the received signal is calculated. To calculate the correlation power at less than one chip rate (e.g., ½ chip rate or ⅓ chip rate), the number of the registers corresponding to the selected rate is required.
As can be seen, the calculations for acquiring the synchronization of the received signal become numerous based on the length of the PN code and chip rate. For example, suppose that the PN code is comprised of 128 bits, and that the correlation power is calculated every one chip. The digital matched filter must perform 256 multiplying calculations (128 calculations for the I signal and 128 calculations for the Q signal), 256 squaring calculations for squaring the results of each multiplying calculation, and summing calculations for summing the results of the squaring calculations at the one chip rate.
Furthermore, since accuracy in acquiring the synchronization is reduced under noisy conditions, the chip rate of less than one chip is necessary. Suppose that the PN code is comprised of 128 bits, and that the correlation power is calculated every {fraction (1/10)} chip. The digital matched filter must perform 2560 multiplying calculations and needs 2560 registers and 2560 multipliers. Thus, the size of the digital matched filter becomes larger as faster calculations are required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved small synchronous detector for acquiring the synchronization of a radio signal speedily and correctly.
It is a further object of the present invention to avoid large digital matched filters when fast calculations are required.
To accomplish these objectives, a synchronous detector used in a CDMA communication receiver comprises a correlator, a pre-synchronous decision circuit, an n-chip correlation coefficient generator and a synchronous estimator. The correlator calculates a plurality of correlation values between a received signal spreading with an x-chip sequence of a spread code and an n-chip correlation coefficient at different phase timing, where x and n are positive integers and n is smaller than x. The pre-synchronous decision circuit, coupled to the correlator, generates at least one timing control signal indicating phase timing corresponding the highest correlation value. The n-chip correlation coefficient generator generates the n-chip correlation coefficient at the phase timing indicated by the timing control signal. The synchronous estimator estimates a synchronous phase by calculating correlation values between the received signal and the n-chip correlation coefficient generated by the n-chip correlation coefficient generator every cycle of the spread code and by accumulating the correlation values.


REFERENCES:
patent: 5832021 (1998-11-01), Kondo
patent: 5881099 (1999-03-01), Takahashi et al.
“A Development Conditions and Its Technical Issue of Digital Matched Filters in Spread-Spectrum Communication Systems” Hisao Tachika, The Institute of Electronics, Information and Communication Engineers, SST92-21 (1992).

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