Synchronous delay circuit for generating synchronous delayed sig

Details Synchronous delay circuit for generating synchronous delayed sig Synchronous delay circuit for generating synchronous delayed sig

1998-04-07

1999-12-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, 327121, 327161, H03B 1900

Patent

active

060054212

ABSTRACT:
In a frequency multiplier circuit, a first delaying section delays a reference signal and generates an output signal when the reference signal has been delayed by a predetermined delay time. A second delaying section generates n (n is an integer more than 0) delayed signals from the reference signal. The first delayed signal of the n delayed signals has a first delay time with respect to the reference signal, and an m-th delayed signal (m is a positive integer and m.ltoreq.n) of the n delayed signal has an m-th delay time with respect to the reference signal. The first through n-th delay times are integer multiples of the first delay time and the predetermined delay time is equal to (n+1) times the first delay time. The second delaying section has a plurality of different input locations for receiving the reference signal and one of the input locations is set to receive the reference signal in accordance with a setting signal from the first delaying section.

REFERENCES:
patent: 5530387 (1996-06-01), Kim
patent: 5684418 (1997-11-01), Yanaguichi
patent: 5789953 (1998-08-01), Au
Shimizu et al., "A Multimedia 32b RISC Microprocessor With 16Mb DRAM", IEEE International Solid-State Circuit Conference, pp. 216-217, (1996).

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