Synchronous delay circuit

Details Synchronous delay circuit Synchronous delay circuit

1998-06-01

2000-06-13

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327166, 327271, 327277, H03L 700

Patent

active

060753951

ABSTRACT:
A synchronous delay circuit contains a first delay circuit for propagating a pulse for a fixed period of time, a second delay circuit for passing the pulse over a length proportional to the length of the first delay circuit along the path that the pulse propagated, and a circuit for outputting a monitor signal when a clock period is propagating through a clock driver. The first delay circuit measures a clock period tCK, and the second delay circuit reconstructs the measured clock period. External clock signals travel through a path from an input buffer through a first switch of a clock driver. The time corresponding to a delay time of the input buffer (td1) and a delay time of the clock divider (td2) is subtracted from the clock period tCK producing a delay circuit with a delay of tCK-(td1+td2). When the clock pulse passes through the delay circuit whose delay is tCK-(td1+td2), the internal clock delay becomes equal to the clock cycle tCK. Thus, the internal clock is free of clock skew.

REFERENCES:
patent: 5287025 (1994-02-01), Nishimichi
patent: 5699003 (1997-12-01), Saeki
patent: 5920222 (1999-07-01), Eustis et al.
J-Man Han et al., "Skew Minimization Techniques for 256M-bit Synchronous DRAM and Beyond", 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 192-193.
Toshio Yamada et al., "Capacitance coupled Bus with Negative Delay Circuit for High speed and Low Power (10GB/s<500mW) Synchronous DRAMs", 1996 Symposium on VLSI Circuits Digest of Tech. Papers, pp. 112-113.
Richard B. Watson, Jr. et al., "Clock Buffer Chip with Absolute Delay Regulation Over Process and Environmental Variations", IEEE 1992 Custom Integrated Circuits Conference, pp. 25.2.1-25.2.5.
Yoshinori Okajima et al., "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE Trans. Electron. vol. E79-C, No. 6, Jun. 1996, pp. 798-807.

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