Synchronous de-skew with programmable latency for multi-lane...

Details Synchronous de-skew with programmable latency for multi-lane... Synchronous de-skew with programmable latency for multi-lane...

2008-07-11

2011-12-06

Phu, Phuong (Department: 2611)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S365000, C375S373000, C375S343000, C375S376000, C713S400000, C713S503000, C370S509000, C370S514000

Reexamination Certificate

active

08073090

ABSTRACT:
A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.

REFERENCES:
patent: 6418537 (2002-07-01), Yang et al.
patent: 7500131 (2009-03-01), Panikkar et al.
JEDEC Standard No. 206, FBDIMM: Architecture and Protocol, JEDEC Solid State Technology Association, Jan. 2007, pp. 1-128.

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