Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device
Reexamination Certificate
2002-02-04
2003-12-09
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using a three or more terminal semiconductive device
C323S284000
Reexamination Certificate
active
06661208
ABSTRACT:
TECHNICAL FIELD
The invention relates to a synchronous dc—dc converter circuit and to a method of operating a synchronous dc—dc converter, as well as to components for use in such a converter.
BACKGROUND AND SUMMARY OF THE INVENTION
Direct current (dc) to dc converters are known in the art, and are generally used to convert from one dc voltage level to another, for example to provide a 1.5V voltage rail from a 12V voltage supply.
One type of converter, a synchronous dc—dc converter, is illustrated schematically in FIG.
1
. An input voltage V
in
is applied between input terminals
2
,
4
. A pair of transistors, here field effect transistors
6
,
8
, are connected between the input terminals
2
,
4
. The transistor
6
adjacent to the input terminal
4
is known as the control FET or high side transistor, and the transistor
8
adjacent to the ground is know as the synchronous (sync) FET or low side transistor. The high side is relatively more positive than the low side, though it is not necessary that either the high or the low side has any particular relationship to ground.
The node between the transistors
6
,
8
is known as the switch node
10
. The switch node feeds through an inductor
12
and across a capacitor
14
to an output
16
.
The control and sync FETs are driven by respective drivers
30
,
32
.
A control circuit
18
has one input on an input control terminal
20
and another input fed from the output
16
via a feedback path
22
. The control circuit
18
supplies control signals to control the FETs
6
,
8
to maintain a constant voltage at the output by switching transistors
6
,
8
off and on alternately. The control signals are alternating signals which cause the control and sync FETs to conduct alternately. The mark-space ratio is varied, i.e. the ratio of the time for which the control FET conducts to the time the sync FET conducts is modulated, to achieve the desired voltage on the output
16
.
Examples of such dc—dc converters include those presented in WO98/49607 to Intel Corporation and U.S. Pat. No. 5,479,089 to Lee.
One feature of synchronous dc—dc converters is that it is not generally desired to switch on both high and low side transistors
6
,
8
simultaneously. If both transistors are on, the input voltage is short-circuited by current passing directly between the two input terminals
2
,
4
through the control and sync FETs. This phenomenon is known as “shoot-through”. Accordingly, the control circuit
18
is generally arranged to ensure that only one of the two transistors
6
,
8
is on at a time.
This is conventionally carried out by monitoring two voltages. The voltage at the switch node
10
is monitored to prevent the switching on of the low side transistor
8
until the high side transistor
6
is switched off. The voltage at the gate
110
of the low side transistor
8
is monitored to prevent the high side transistor switching on until the low side transistor
8
is switched off. WO98/49607 describes a circuit of this type, as does U.S. Pat. No. 5,479,089 to Lee.
The dead time when neither FET is conducting depends on the transistor threshold voltage and the capacitance of the sync FET, which vary widely due to manufacturing spread of parameters of the chosen FET, as well as according to the individual choice of FET. This means that a control IC has to use conservative estimates of these parameters to produce a dead time that will avoid shoot through. This is generally a longer dead time than would be possible if the control circuit were optimised for the specific FETs used.
The present trend is to increase switching and clock speeds, which increases the significance of the dead time during which neither high or low side transistor
6
,
8
is on. It would be beneficial to reduce this time.
A further disadvantage occurs in the case that a plurality of FETs in parallel are used in place of the single high and low side transistors. The parallel FETs never switch at exactly the same time due to different gate resistances and other parameters caused again by manufacturing variations or variability in the circuit in which the FETs are provided. Thus, it becomes difficult to correctly determine when all of the high side or low side FETs are switched off and accordingly when the other FETs can be switched on. The solution generally adopted is to include a gate resistor in the circuit, but this slows down the switching of the MOSFETs and increases switching losses, especially at high frequencies. Accordingly, it would be beneficial to provide a circuit arrangement that could more easily use parallel FETs.
According to the invention there is provided a synchronous dc—dc converter circuit for converting an input dc voltage of predetermined polarity to an output dc voltage, the synchronous dc—dc converter circuit comprising a dc input and a ground input for supplying the input dc voltage; a control FET having source and drain connected between the dc input and a switch node, the switch node being for connection through an inductor to an output; a sync FET having source and drain connected between the switch node and the ground input; a switching input for inputting an alternating control signal;
a comparator for detecting a voltage change on the switch node of opposite polarity to the dc input voltage and sending out a trigger signal in response; and at least one driver for driving the control and sync FETs alternately in response to the alternating control signal on the switching input,
wherein the driver, in response to a change in the alternating control signal of a predetermined polarity, switches off the sync FET, and then waits for the trigger signal before switching on the control FET.
The arrangement is efficient at reducing dead time. Further, the arrangement works with a variety of FETs and whether or not the FETs are used in parallel.
Preferably, the voltage on the switch node is used to control both the control and the sync FETs to avoid shoot through.
In particular, a comparator may be provided to trigger a signal to switch the next FET on when the switch node voltage falls below a predetermined value. The comparator may function as an edge detector, for example by being a.c. coupled to the switch node through a capacitor.
The predetermined value may be of opposite sign to the dc input voltage.
The same predetermined value may be used for both the control and the sync FETs.
The control FET may be packaged together with a driver, and the sync FET may be provided in a separate package likewise with its driver. Both drivers may be responsive to the voltage of the switch node to determine when the FET can be switched on. This avoids any need for connection between the two packages, apart from the switching signal input, since the switch node voltage is available to both packages.
Previously, where separate control and sync FET driver packages have been provided there has been a need for interconnection between the packages to pass information related to the sync FET gate voltage to the control FET driver to avoid shoot-through. By using the switch node voltage to control both FETs, this need is avoided.
The invention also relates to a high side component for a synchronous dc—dc converter circuit for converting an input dc voltage of predetermined polarity to an output dc voltage, the high side component comprising: a dc input for supplying the input dc voltage; a control FET having source and drain connected between the dc input and a switch node, the switch node being for connection through an inductor to an output; a switching input for inputting an alternating control signal; an edge detector for detecting an edge on the switch node of opposite polarity to the dc input voltage and sending out a trigger signal in response; and at least one driver for driving the control FET in response to the alternating signal on the switching input wherein in response to a change in polarity of the alternating signal of first predetermined sign the driver switches off the control FET and in response to a change in polarity of the alternating signa
De Groot Leonardus
Rutter Philip
Wheeler Nicolas J.
Biren Steven R.
Koninklijke Philips Electronics , N.V.
Riley Shawn
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