Synchronous data transmission method and device implementing sam

Details Synchronous data transmission method and device implementing sam Synchronous data transmission method and device implementing sam

1985-05-20

1987-07-21

Smith, Jerry

Excavating

371 49, 375 19, H03K 526, G08C 2500

Patent

active

046823344

ABSTRACT:
A synchronous data transmission method uses an MB 1C 1F type binary-binary code in which the binary data to be transmitted is subdivided into successive blocks of M bits complemented when they feature a disparity (marks minus spaces) of the same sign as the data already encoded, to which is added a complement bit indicating if complementing has been applied and a frame bit consisting of a parity bit enabling the subdivision into blocks carried out at the encoding stage to be recovered at the decoding stage. The encoder has at the input a demultiplexer carrying out the subdivision into blocks followed by circuits for computing the word digital sum and parity and the running digital sum, together with an inverter circuit which processes the blocks from the multiplexer and their parity bit under the control of a complementing decision circuit and a multiplexer transforming the encoded binary signal from the inverter circuit into an isochronous sequence to which a frame bit is added.

REFERENCES:
patent: 3631471 (1971-12-01), Griffiths
patent: 3646517 (1972-02-01), Waters
patent: 3840854 (1974-10-01), Franaszek
patent: 4264972 (1981-04-01), Drullmann
patent: 4309694 (1982-01-01), Henry
patent: 4502143 (1985-02-01), Kato

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