Synchronous data serialization circuit

Details Synchronous data serialization circuit Synchronous data serialization circuit

2001-07-19

2003-09-02

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C341S100000

Reexamination Certificate

active

06614371

ABSTRACT:

BACKGROUND
This invention relates to integrated circuits utilized for data processing applications. More particularly, the present invention relates to a data processing circuit and method for serializing data.
Integrated circuits are commonly utilized in digital and mixed signal systems for processing data. For example, integrated circuits typically form the basic building blocks for computer systems, digital data communications systems, and industrial data processing systems as well as other electronic systems. One particular example of a digital data communication system that may benefit from advanced data processing techniques is a telecommunication system such as a serial optical network (“SONET”) system.
The rise of the information age has put ever increasing demands on integrated circuits used to process data. For example, systems previously designed to carry only sound, such as the telephone system, are now being designed to carry digital and mixed signal data between both individual users and large data processing networks such as computer networks. As more users store and communicate data using data networks, more and more data must be processed by the integrated circuits that are used to build the data processing systems. Accordingly, to keep up with the increasing data processing demands, integrated circuits must be designed to process data at ever increasing speeds.
Integrated circuits used for data processing applications commonly require that data from a variety of different data sources be combined and transmitted over a single data line. For example, many systems require that parallel digital data signals be combined and transmitted serially over a single data line to another part of the system. A common circuit used to perform such a task is a serializer or multiplexer.
FIG. 1
illustrates a functional diagram of a typical multiplexer commonly used and well known in the art. The multiplexer
100
includes input lines D
0
and D
1
for receiving data Din
0
and Din
1
, a select line for receiving a select control signal, and an output line. The multiplexer couples only one of the input lines to the output line in accordance with the particular state of the select control signal. For a 2-input multiplexer, the select line may receive a binary logic signal for coupling each of the input lines to the output line.
However, as the speed of data processing systems increases, traditional multiplexer circuits used to serialize data may fail to work effectively. For example, one problem is that the multiplexer circuitry must be designed and timed such the data received on each of the input lines of the multiplexer is available at the output of the multiplexer when the particular input line is selected by the select line. If the timing of the data received on each of the multiplexer inputs and the control signals received on the select line are not precisely controlled, then the output may contain erroneous data, and the system will not work.
Therefore, what is needed is a data processing system and method that can serialize data at very high frequencies. Additionally, what is needed is a synchronous data serialization circuit that can process data from multiple data sources at very high frequencies.
SUMMARY
In accordance with the present invention a data processing circuit includes a first data path for processing first data, the first data path including a first data storage circuit, a second data path for processing second data, the second data path including a second data storage circuit, a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path, the multiplexer having a select input coupled to a clock signal, and a delay circuit configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
In one embodiment, the first data storage circuit is a flip-flop that receives and stores the first data in response to a clock signal making a transition in a first direction, such as the rising edge of a clock, for example. Additionally, in one embodiment, the second data storage circuit is a flip-flop that receives and stores the second data in response to a clock signal making a transition in a second direction opposite the first direction, such as the falling edge of a clock, for example. Furthermore, in one embodiment, the delay circuit is configured to receive the second data on a first input and transmit delayed second data to an input of the second data storage circuit.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.


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