Synchronous data receiver circuit

Details Synchronous data receiver circuit Synchronous data receiver circuit

1985-06-20

1987-08-11

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375116, 375118, 371 47, H04L 708

Patent

active

046866906

ABSTRACT:
The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on.

REFERENCES:
patent: 4187394 (1980-02-01), Sievers
patent: 4225960 (1980-09-01), Masters
patent: 4507779 (1985-03-01), Barner, Jr. et al.
"Recurrent Codes: Easily Mechanized Burst-Correcting, Binary Codes" Hazelbarzer, B.S.T.J., Jul. 1959.

Affiliated with

Also associated with

Rating

Synchronous data receiver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous data receiver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous data receiver circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-407652