Synchronous data processing system having arithmetic and control

Details Synchronous data processing system having arithmetic and control Synchronous data processing system having arithmetic and control

1974-12-27

1977-05-31

Chapnick, Melvin B.

Communications: electrical

Digital comparator systems

G06F 738, G06F 906, G06F 1300

Patent

active

040272923

ABSTRACT:
A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.

REFERENCES:
patent: 3328566 (1967-06-01), Kinzie et al.
patent: 3331954 (1967-07-01), Kinzie et al.
patent: 3387273 (1968-06-01), Carter et al.
patent: 3555516 (1971-01-01), Proctor
patent: 3686490 (1972-08-01), Goldstone
patent: 3755784 (1973-08-01), Greek, Jr. et al.
patent: 3890600 (1975-06-01), Roche
patent: 3899667 (1975-08-01), Simone

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