Synchronous data interface circuit and method of equalizing sync

Details Synchronous data interface circuit and method of equalizing sync Synchronous data interface circuit and method of equalizing sync

1992-06-09

1995-03-28

Chin, Stephen

Pulse or digital communications

Equalizers

333 18, 375377, H03H 730

Patent

active

054024447

ABSTRACT:
A synchronous data interface circuit which is reduced in scale and low in power consumption is provided. A bit clock amplitude detector measures the amplitude of a bit clock signal transmitted thereto through a signal line and outputs to a set of equalizers a signal representing a ratio corresponding to the measured amplitude. The equalizers also respectively receive an NRZ data signal, a frame signal and a bit clock signal on lines of the same length and made of the same material. The equalizers thus individually set equalizing amounts and compensate for amplitude distortion of the individual signals. In this instance, each equalizing amount is set in accordance with the signal received from the bit clock amplitude detector. Discriminators receive signals after this amplitude compensation and reproduce the original signals as output.

REFERENCES:
patent: 4811423 (1989-03-01), Eastmond
patent: 5134722 (1992-07-01), Emslie et al.
patent: 5163066 (1992-11-01), Cupo et al.

Affiliated with

Also associated with

Rating

Synchronous data interface circuit and method of equalizing sync does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous data interface circuit and method of equalizing sync, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous data interface circuit and method of equalizing sync will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2257115