Synchronous cycle steal mechanism for transferring data between

Details Synchronous cycle steal mechanism for transferring data between Synchronous cycle steal mechanism for transferring data between

1981-10-13

1984-10-23

Thomas, James

Boots, shoes, and leggings

G06F 300

Patent

active

044791798

ABSTRACT:
A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit. This new cycle steal mechanism is the reverse of the normal situation where it is the microprocessor or DMA unit that is controlling the cycle stealing. This new cycle steal mechanism makes use of the microprocessor address set-up pulse (ALE) and the DMA unit address set-up pulse (ADSTB) to cause the cycle stealing of the data to or from the controller storage unit to occur during such address set-up time.

REFERENCES:
patent: 3961312 (1976-06-01), Bodner
patent: 3972023 (1976-07-01), Bodner
patent: 3996564 (1976-12-01), Kerrigan
patent: 4038642 (1977-07-01), Bouknecht
patent: 4096578 (1978-06-01), Malkemes
patent: 4128876 (1978-12-01), Ames et al.
patent: 4131944 (1978-12-01), Mager
patent: 4181934 (1980-01-01), Marenin

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