Synchronous counter terminal count output circuit

Details Synchronous counter terminal count output circuit Synchronous counter terminal count output circuit

1991-02-07

1992-07-28

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307594, 307445, H03K 1716, H03K 513

Patent

active

051343150

ABSTRACT:
A synchronous counter flip flop circuit (20) incorporates a logical AND input circuit (22) having multiple inputs (24) and a first output (25) delivering a first count signal upon concurrence of count logic signals at count logic signal inputs (BIT0-BIT7) with a count enable clock signal at a count enable clock signal input (CET). A count delay circuit (30) is coupled to the first output (25) to provide a second output (32) in parallel with the first output (25) for delivering a delayed second count signal. A logical AND intermediate circuit coupling (34) having first and second inputs coupled respectively to the first and second outputs (25,32) provides a third output (35) delivering a third count signal which is a filtered intermediate terminal count signal (TC). An inverting output buffer circuit (26) provides a final inverted filtered terminal count signal (TC) at the final terminal count output (28). The delay circuit (30) is constructed to provide a selected delay time interval longer than the transient duration time interval of decoding noise spikes for filtering out the decoding noise spikes at the logical AND intermediate circuit coupling (34).

REFERENCES:
patent: 4757214 (1988-07-01), Kobayashi
patent: 5019724 (1991-05-01), McClure
patent: 5023486 (1991-06-01), Gongwer
patent: 5036221 (1991-07-01), Brucculeri et al.

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