Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1975-02-18
1976-07-20
Zazworsky, John
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307224R, 328 41, 328 42, H03K 2100
Patent
active
039708675
ABSTRACT:
A plural bit-stage synchronous counter/divider wherein each bit-stage comprises four multiple-input inverting gates in flip-flop configuration with the output of the first and second gates connected to one of the multiple inputs of the third and fourth gates respectively, one of the inputs of each of said first and second gates connected to a clock pulse line, the outputs of said third and fourth gates connected to a second input of said multiple inputs of each of said second and fourth gates and of said first and third gates respectively and third inputs of said multiple inputs of said third and fourth gates connected to clear and preset lines respectively and a clock pulse generator means providing clock pulses of a length between one and two times the propagation delay period of the slowest of said gates.
REFERENCES:
patent: 3467839 (1969-09-01), Miller
patent: 3535544 (1970-10-01), De Troye
Maley, IBM Technical Disclosure Bulletin, vol. 2, No. 2, Aug. 1959, p. 63.
Control & Instrumentation, N. Watson, Nov. 1972, vol. 4, No. 10, pp. 46, 47.
Comfort James T.
Dixon James O.
Levine Harold
Rasco Marcus S.
Texas Instruments Incorporated
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