Synchronous CMOS rectifying circuit for step-up devices

Details Synchronous CMOS rectifying circuit for step-up devices Synchronous CMOS rectifying circuit for step-up devices

2000-07-05

2001-10-30

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

In shunt with source or load

Using choke and switch across source

Reexamination Certificate

active

06310466

ABSTRACT:

TECHNICAL FIELD
This invention relates to a synchronous CMOS rectifying circuit for step-up devices and to a method of carrying out a DC/DC conversion by means of the rectifying circuit.
More particularly, the invention deals with a family of high-efficiency synchronous circuits for switching control that can be operated in the step-up mode even at very low (around 0.8 V) supply voltages and very small idle currents.
BACKGROUND OF THE INVENTION
Considerable research work is being conducted in the field of synchronous rectifying circuits, specifically for step-up devices, which can be operated at very low (e.g., 0.8 V) supply voltages and very small idle currents.
The demand for rectifiers with such features comes especially from those applications where battery-powered apparatuses, such as pagers, cellular phones, portable computers, and more generally long-range portable apparatuses, require that the conversion of a battery voltage to a stabilized voltage of a higher value be carried out in a most efficient manner.
A general trend in the design of such rectifiers provides for the use of active switch elements having very low internal resistance and a high switching rate, and the use, as active elements, of field-effect transistors or bipolar transistors in place of the loop-back diodes employed in the past. The class of converters thus produced are known as synchronous rectifying converters, also on account of a control logic being provided therein which is effective to perfectly synchronize the opening and closing of the switch elements and prevent simultaneous activation (cross-conduction) from occurring, as this would result in large power dissipation or unacceptably poor performance.
A synchronous rectifying circuit ideally should be capable of operating with very low supply voltages and of minimizing cross-conduction losses as the switch elements are turned on simultaneously.
Additional features expected of such an ideal rectifier include the following: it should produce full disconnection of the output load from the electrical source in a shut-down situation and with an output voltage Vout=0; it should dampen out the oscillation that appears as the inductor is fully discharged due to the presence of parasitic capacitances in the switch elements (damped ringing); it should enhance the converting efficiency of the circuit; and it should automatically clamp the internal supply voltage of the circuit to the highest available potential (self-bootstrapping).
Shown by way of example in
FIG. 1
is a schematic diagram of a prior art synchronous rectifying circuit
20
as applied to a step-up topology. The circuit has an input terminal IN which is supplied a voltage Vin, and has an output terminal OUT which is connected to an electric load. The circuit
20
uses a P-channel Power-MOS
11
for a switch element. A control logic
13
controls the sequencing and times the actuations of a switch
14
and the switch
11
through respective outputs
17
and
16
. By using an active device for the switch element
11
, a smaller voltage drop can be obtained in transferring power to the load.
A sensing element
18
adapted to sense the current being transferred to the load is provided for a compare block
12
, which is arranged to control the transfer of power and send a suitable signal to the control logic
13
through an input
15
.
The signal from the compare block
12
effectively prevents the Power-MOS
11
from also transferring power from the load to the input IN, thus reversing the current direction and defeating all attempts at improved efficiency.
The determination to use a P-channel Power-MOS for a switch element is justified by the low internal resistance of Power-MOSs and the ability to use a voltage-oriented rather than current-oriented drive. Unfortunately, the presence of the Power-PMOS body connection introduces, as shown in
FIG. 1
, a large-size diode across the input and output terminals of the circuit
20
. At start-up, when the output voltage is still close to zero, this large diode allows an inrush of current whose maximum value can be far above the peak value during steady-state operation and which can detrimental effects on the passive components (e.g., inductor
18
), unless the latter are provided oversize to accommodate this initial transient phase.
An attempt to depress the maximum value of the inrush current by the use of a limiting resistor admittedly would safeguard the components, but also result in unacceptably large power losses.
Lastly, the presence of the parasitic diode makes adjusting the output voltage to values below Vin−V
BE
(step-down configuration) impracticable.
Another approach to providing a highly efficient synchronous rectifier is shown in FIG.
2
and described in European Patent Application No. 97830740.3 by this Applicant, and herein specifically incorporated by reference in toto.
Shown in that Figure is a synchronous rectifier
30
which includes a bipolar transistor
7
as a switch element. A rectifier block
2
includes a control logic
5
which is connected to all the terminals
3
,
4
of the transistor
7
and receives the supply voltage Vin on an input
6
.
A second switch element
1
is provided which is formed with MOS technology and incorporates a control logic
10
.
While in many ways advantageous, this solution is inadequate to remove all the ringing and minimize the losses from cross-conduction.
A further prior approach is shown schematically in FIG.
3
. This is a synchronous rectifying circuit
19
manufactured by Maxim Semiconductors. This circuit cannot be operated at lower voltages than 1.7 V.
To summarize, all of the prior art solutions, although providing highly efficient step-up converters, still have limitations and deficiencies, including complex control logic circuitry, inability to operate with low supply voltages, possible cross-conduction side effects, and inability to operate in a step-up/step-down combined mode.
Until now, no high-efficiency rectifying circuit, particularly intended for step-up/step-down applications, was available that provided a uniquely simple construction combined with outstanding performance in terms of ringing suppression and full disconnection of the load in the shut-down mode.
SUMMARY OF THE INVENTION
Embodiments of the invention use, as the gist of the synchronous rectifier, a MOS type of power transistor which can suppress the ringing effect and ensure full shutting down of the load.
Presented, therefore is a synchronous CMOS rectifying circuit that has an input terminal and an output terminal for converting a DC input voltage into a DC output voltage. The rectifying circuit includes an inductor selectively coupled to the input terminal, and a first electronic switch to selectively control the coupling of the inductor. The rectifying circuit also includes a MOS power transistor for coupling the inductor to the output terminal, and a biasing circuit for biasing a body terminal of the MOS power transistor with one of the voltages that it receives at a first bias input or a second bias input. In one embodiment the first bias input is coupled to the input terminal and the second bias input is coupled to the output terminal. The MOS power transistor has a first conduction terminal connected to a terminal of the inductor, a second conduction terminal coupled to the output terminal of the rectifier, and is driven at a control terminal by a control logic circuit effective to sense a difference in electric potential between at least one conduction terminal of the MOS power transistor and the body terminal of the MOS power transistor.
Also presented is a method of converting a DC input signal presented on an input terminal into a DC output signal presented on an output terminal of a converting/rectifying circuit. The method uses a first electronic switch to selectively couple the inductor to the input terminal for transferring energy from the input terminal to the output terminal, and includes a MOS power transistor. The MOS power transistor, that is coupled between the input a

Affiliated with

Also associated with

Rating

Synchronous CMOS rectifying circuit for step-up devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous CMOS rectifying circuit for step-up devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous CMOS rectifying circuit for step-up devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2600641