Synchronous clock regenerator for binary serial data signals

Details Synchronous clock regenerator for binary serial data signals Synchronous clock regenerator for binary serial data signals

1980-06-25

1983-11-15

Shaw, Gareth D.

Boots, shoes, and leggings

364200, G06F 728, G06F 506

Patent

active

044159846

ABSTRACT:
Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit. Thereafter, and until the next framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the l-of-n selector.

REFERENCES:
patent: 4034348 (1977-07-01), Rathbun
patent: 4034352 (1977-07-01), Hotchkiss
patent: 4048481 (1977-09-01), Bailey, Jr. et al.
patent: 4056851 (1977-11-01), Hovagimyan et al.

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