Synchronous clock multiplexer

Details Synchronous clock multiplexer Synchronous clock multiplexer

1996-10-08

1999-05-11

Chan, Jason

Pulse or digital communications

Synchronizers

370537, 331 49, H04L7/00

Patent

active

059036168

ABSTRACT:
A clock multiplexer including a plurality of clock selection circuits. Each clock selection circuit determines if a clock input is selected and provides the clock input to a clock output based on the determination. Each clock selection circuit further includes deselect inputs, and a select input which is coupled to a deselect output, the deselect output providing a signal indicating if the select input is active. Each deselect input is connected to a respective one of the deselect outputs from the other clock selection circuits. In each clock selection circuit, the clock input is not provided to the clock output when one of the deselect inputs is active.

REFERENCES:
patent: 4853653 (1989-08-01), Maher
patent: 4855616 (1989-08-01), Wang et al.
patent: 4970405 (1990-11-01), Hagiwara
patent: 5045714 (1991-09-01), Park et al.
patent: 5231389 (1993-07-01), Yamauchi
patent: 5237573 (1993-08-01), Dhuey et al.
patent: 5418407 (1995-05-01), Frenkil
patent: 5648964 (1997-07-01), Inagaki et al.

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