Synchronous clock generator including a delay-locked loop...

Details Synchronous clock generator including a delay-locked loop... Synchronous clock generator including a delay-locked loop...

1999-05-20

2001-03-13

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S155000

Reexamination Certificate

active

06201424

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to the field of integrated circuits and, more particularly, to the generation of clock signals for controlling the operation of such circuits.
2. Description of the Background
Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc. rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and SLD RAM require individual parts to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important.
Typically, operations are initiated at the edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge.
One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90°, 180° and 270°, respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations.
An example of such an approach is shown in
FIG. 1
where the timing of operations in a memory device
10
is defined by an externally provided reference control clock signal CCLKREF and an externally provided reference data clock signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in a memory controller
11
and transmitted to the memory device
10
over a control clock bus
13
and a data clock bus
14
, respectively. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the reference control clock signal CCLKREF is a continuous signal and the reference data clock signal DCLKREF is a discontinuous signal, i.e., the reference data clock signal DCLKREF does not include a pulse for every clock period. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time upon arrival at the memory device
10
due to differences in propagation times, such as may be produced by routing differences between the control clock bus
13
and the data clock bus
14
.
Control data CD
1
-CDN arrive at respective input terminals
16
substantially simultaneously with pulses of the reference control clock signal CCLKREF and are latched in respective control data latches
18
. However, if the device attempts to latch the control data CD
1
-CDN immediately upon the edge of the reference clock signal CCLKREF, the control data may not have sufficient time to develop at the input terminals
16
. For example, a voltage corresponding to a first logic state (e.g., a “0”) at one of the input terminals
16
may not change to a voltage corresponding to an opposite logic state (e.g., a “1”) by the time the data are latched. To allow time for the control data CD
1
-CDN to fully develop at the input terminals
16
, the control data are latched at a delayed time relative to the reference control clock signal CCLKREF. To provide a clock edge to trigger latching of the control data CD
1
-CDN at the delayed time, a delay circuit
20
delays the reference clock signal CCLKREF by a delay time to produce a first delayed clock signal CCLKD. Edges of the first delayed clock signal CCLKD activate the control data latches
18
to latch the control data CD
1
-CDN.
Data DA
1
-DAM arrive at data terminals
22
substantially simultaneously with the reference data clock signal DCLKREF. Respective data latches
24
latch the data DA
1
-DAM. As with the control data CD
1
-CDN, it is desirable that the data DA
1
-DAM be latched with a slight delay relative to transitions of the reference data clock DCKLREF to allow time for signal development at the data terminals
22
. To provide a delayed clock edge, a delay circuit
26
delays the reference data clock signal DCLKREF to produce a phase-delayed data clock DCLKD that is delayed relative to the reference data clock signal DCLKREF.
For latching both control data CD
1
-CDN and data DA
1
-DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clocks CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data, respectively. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CD
1
-CDN or data DA
1
-DAM relative to the clock signals CCLKREF, DCLKREF of the memory device
10
.
One possible approach to producing a variable delay is for the control clock generator to employ a delay-locked loop
28
driven by the external reference clock CLKREF, as shown in FIG.
2
. The reference clock signal CLKREF is input to a conventional, multiple output, variable delay line
30
such as that described in Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,”
IEEE Journal of Solid
-
State Circuits
31(11):1723-1732, November 1996. The delay line
30
is a known circuit that outputs multiple delayed signals CLK
1
-CLKN with increasing lags relative to the reference signal CLKREF. The delays of the signals CLK
1
-CLKN are variably responsive to a control signal Vcon received at a control port
32
.
A feedback path, formed by a comparator
34
and an integrator
36
, produces the control signal Vcon. The feedback path receives the reference clock signal CLKREF at one input of the comparator
34
and receives one of the output signals CLKN from the delay line
30
as a feedback signal at the other input of the comparator
34
. The comparator
34
outputs a compare signal Vcomp that is integrated by the integrator
36
to produce the control signal Vcon.
As is known, the control signal Vcon will depend upon the relative phases of the reference clock signal CLKREF and the feedback signal CLKN. If the feedback signal CLKN leads the reference clock signal CLKREF, the control signal Vcon increases the delay of the delay line
30
, thereby reducing the magnitude of the control signal Vcon until the feedback signal CLKN is in phase with the reference signal CLKREF. Similarly, if the feedback signal CLK lags the reference signal CLKREF, the control signal Vcon causes the delay line
30
to decrease the delay until the feedback signal CLKN is in phase with the reference signal CLKREF.
In the process of acquiring lock, or if the delay-locked loop
28
is disturbed by an unwanted transient on the power supply, temporary interruption of clock signal, etc., the control voltage Vcon may drive the delay line
30
to the point where the delay line
30
no longer passes a signal. That may occur because voltage-controlled delay lines are generally low-pass devices. More delay causes the cutoff frequency to drop. If that occurs, the phase detector may hang in a state that forces the control voltage to remain at a level which prevents signal transmission through the voltage-controlled delay line
30
. The loop
28
will be hung up, with no output clock signals being produced. Should that occur, it is imperative that the condition be rectified as soon as possible. Thus, there is a need for a loss of signal detector which may detect hang up of the loop
28
and take, or initiate, corrective action.
SUMMARY OF THE INVENTION
The present invention is directed to a loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal. The detector

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